From patchwork Sat Oct 17 17:23:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 531818 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 90F18140273 for ; Sun, 18 Oct 2015 04:26:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=gCtHCW1q; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753320AbbJQR0W (ORCPT ); Sat, 17 Oct 2015 13:26:22 -0400 Received: from mail-wi0-f176.google.com ([209.85.212.176]:37779 "EHLO mail-wi0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932444AbbJQRYK (ORCPT ); Sat, 17 Oct 2015 13:24:10 -0400 Received: by wicfv8 with SMTP id fv8so28245163wic.0; Sat, 17 Oct 2015 10:24:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mckOk7XkLJJDldzrqUyrvaKnZSj45owqLJ/QjamuAmY=; b=gCtHCW1qaSDa97Fey/A6eUc7MBDi6C/9ngoiDzZNR2AbjOLkUZ04QnrkmaDxGYecsQ KS8q5M9oyI7JcmtGeWgkxNZpFRC3ejBFoiVitSllVmqgD/5A+z5lahV0vNnN2pI96N+b jH3S1+CPN716F7lWDrE+IWL08llFOHSRpvMC3jvRrGP8Xr2kwziVN/FUF7QKnqMOi/Fr XJgnXBMIrPkFfSEbFK7QcQQ2uHV6vj4sYHJ/Z9ukKNGGe2COe49WTCSAuKtDRB1d0MiU FcMAKtpX1BgDp17Izd91Gz/T4/J7m+Al8GsLVarTt3zJnGM6PidJE5WrKBOpDx6kdROV XVwQ== X-Received: by 10.194.216.228 with SMTP id ot4mr23871316wjc.156.1445102648589; Sat, 17 Oct 2015 10:24:08 -0700 (PDT) Received: from lmecul0520.st.com. (101.210.139.88.rev.sfr.net. [88.139.210.101]) by smtp.gmail.com with ESMTPSA id gh9sm29409201wjb.27.2015.10.17.10.24.07 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 17 Oct 2015 10:24:08 -0700 (PDT) From: Maxime Coquelin To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Linus Walleij , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, afaerber@suse.de, devicetree@vger.kernel.org, Daniel Thompson , bruherrera@gmail.com Subject: [PATCH 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl Date: Sat, 17 Oct 2015 19:23:54 +0200 Message-Id: <1445102638-11575-6-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445102638-11575-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1445102638-11575-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Maxime Coquelin --- Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 7b4800c..dd95bec 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -13,6 +13,9 @@ Required properies: - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to gpio-bank node (children). + - interrupt-parent: phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + - st,syscfg: phandle of the syscfg node used for IRQ mux selection. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins.