From patchwork Wed Oct 14 12:55:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 530171 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id AE503141107 for ; Thu, 15 Oct 2015 00:12:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753515AbbJNNMN (ORCPT ); Wed, 14 Oct 2015 09:12:13 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:39264 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752025AbbJNNML (ORCPT ); Wed, 14 Oct 2015 09:12:11 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NW701E3VOOARSC0@mailout3.samsung.com>; Wed, 14 Oct 2015 22:12:10 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.122]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id C4.52.05342.9A45E165; Wed, 14 Oct 2015 22:12:10 +0900 (KST) X-AuditID: cbfee690-f794e6d0000014de-67-561e54a9d2c0 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 13.2C.18629.9A45E165; Wed, 14 Oct 2015 22:12:09 +0900 (KST) Received: from exypnos.sisodomain.com ([107.108.73.28]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NW700IYZOBSF650@mmp1.samsung.com>; Wed, 14 Oct 2015 22:12:09 +0900 (KST) From: Alim Akhtar To: linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: JBottomley@odin.com, vinholikatti@gmail.com, amit.daniel@samsung.com, essuuj@gmail.com, devicetree@vger.kernel.org, alim.akhtar@samsung.com, arnd@arndb.de Subject: [PATCH v4 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller Date: Wed, 14 Oct 2015 18:25:50 +0530 Message-id: <1444827351-24128-11-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1444827351-24128-1-git-send-email-alim.akhtar@samsung.com> References: <1444827351-24128-1-git-send-email-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCLMWRmVeSWpSXmKPExsWyRsSkSndViFyYwab1XBYP5m1js2i4GmLx d9Ixdov5R86xWiy/sITJ4v/62ywWl3fNYbPovr6DzWLHwioHTo/fvyYxeuycdZfd4/CPH8we fVtWMXp83iQXwBrFZZOSmpNZllqkb5fAlbHx8UbGgl/aFb2Tm9gbGM8odTFyckgImEj8PN/N BmGLSVy4tx7MFhJYwSjRf0oNpubt0w0sXYxcQPGljBJbp89mhHB+Mkr8+b+TBaSKTUBb4u70 LUwgtoiAjcT5mw+YQIqYBRYxSnx4PA8sISyQJTH/wn12EJtFQFWid8YDZhCbV8BDYu3pH+wQ 6xQlup9NADuDEyg+d/4xdoiT3CXaj08HGyohsI5dYueMdUwQgwQkvk0+BHQFB1BCVmLTAWaI OZISB1fcYJnAKLyAkWEVo2hqQXJBcVJ6kYlecWJucWleul5yfu4mRmDgn/73bMIOxnsHrA8x CnAwKvHwZqyWDRNiTSwrrsw9xGgKtGEis5Rocj4wvvJK4g2NzYwsTE1MjY3MLc2UxHlfS/0M FhJITyxJzU5NLUgtii8qzUktPsTIxMEp1cDIJnAn0vrg9ZX9ne+OrLyse1sw7f6ev4or8/oW rGR92eAVyn6+YwZf1dNlKcosZ6dlsSxWK7sgWf1PwU+vOEH3zYTqB7uK66+eEgxh2X1msV9l m/7yBa0trNtXleR8DOSc+ch0QedCVpaPe0WuGgZbp0rWtGQe+G45g9PUaeGMyxl7mk9qXmBV YinOSDTUYi4qTgQAcl1nhncCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrEIsWRmVeSWpSXmKPExsVy+t9jAd2VIXJhBpuarCwezNvGZtFwNcTi 76Rj7Bbzj5xjtVh+YQmTxf/1t1ksLu+aw2bRfX0Hm8WOhVUOnB6/f01i9Ng56y67x+EfP5g9 +rasYvT4vEkugDWqgdEmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE31VbJ xSdA1y0zB+geJYWyxJxSoFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYGaCBhDWPGxscbGQt+ aVf0Tm5ib2A8o9TFyMkhIWAi8fbpBhYIW0ziwr31bF2MXBxCAksZJbZOn80I4fxklPjzfydY FZuAtsTd6VuYQGwRARuJ8zcfMIEUMQssYpT48HgeWEJYIEti/oX77CA2i4CqRO+MB8wgNq+A h8Ta0z/YIdYpSnQ/m8AGYnMCxefOPwYWFxJwl2g/Pp1pAiPvAkaGVYwSqQXJBcVJ6blGeanl esWJucWleel6yfm5mxjB8fVMegfj4V3uhxgFOBiVeHgzVsuGCbEmlhVX5h5ilOBgVhLh/WMg FybEm5JYWZValB9fVJqTWnyI0RTosInMUqLJ+cDYzyuJNzQ2MTc1NrU0sTAxs1QS571xiCFM SCA9sSQ1OzW1ILUIpo+Jg1OqgZHz/SGbxL1PJv2tmr0k8cBxs8IDpmqZbf6vj5f+mhkeeXdy e4vAmotXl4rPyT8m1r1HoXW6e5dhw4/WY/9/zL5WUnNU4vLvp01pxpGVzz+fC2O6+8DPRbqc OaH0F/csl/uPSxmkMpYd85ob2qyyLXzbxT1iNxZ7LdmodEN7/+tPxYq+d3fOqrBXYinOSDTU Yi4qTgQAPUutH8UCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Seungwon Jeon This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings. Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar --- .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt new file mode 100644 index 000000000000..042dedf4e323 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt @@ -0,0 +1,104 @@ +* Exynos Universal Flash Storage (UFS) Host Controller + +UFSHC nodes are defined to describe on-chip UFS host controllers. +Each UFS controller instance should have its own node. + +Required properties: +- compatible : compatible name, contains "samsung,exynos7-ufs" +- interrupts : +- reg : Should contain HCI, vendor specific, UNIPRO and + UFS protector address space +- reg-names : "hci", "vs_hci", "unipro", "ufsp"; + +Optional properties: +- vdd-hba-supply : phandle to UFS host controller supply regulator node +- vcc-supply : phandle to VCC supply regulator node +- vccq-supply : phandle to VCCQ supply regulator node +- vccq2-supply : phandle to VCCQ2 supply regulator node +- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V + or 2.7-3.6V. This boolean property when set, specifies + to use low voltage range of 1.7-1.95V. Note for external + UFS cards this property is invalid and valid VCC range is + always 2.7-3.6V. +- vcc-max-microamp : specifies max. load that can be drawn from vcc supply +- vccq-max-microamp : specifies max. load that can be drawn from vccq supply +- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply +- -fixed-regulator : boolean property specifying that -supply is a fixed regulator + +- clocks : List of phandle and clock specifier pairs +- clock-names : List of clock input name strings sorted in the same + order as the clocks property. + "core", "sclk_unipro_main", "ref" and ref_parent + +- freq-table-hz : Array of operating frequencies stored in the same + order as the clocks property. If this property is not + defined or a value in the array is "0" then it is assumed + that the frequency is set by the parent clock or a + fixed rate clock source. +- pclk-freq-avail-range : specifies available frequency range(min/max) for APB clock +- ufs,pwr-attr-mode : specifies mode value for power mode change, possible values are + "FAST", "SLOW", "FAST_auto" and "SLOW_auto" +- ufs,pwr-attr-lane : specifies lane count value for power mode change + allowed values are 1 or 2 +- ufs,pwr-attr-gear : specifies gear count value for power mode change + allowed values are 1 or 2 +- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change + can be one of "HS_rate_b" or "HS_rate_a" +- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values + 3 timers supported + +- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values + 3 timers supported + +- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY, + this is a boolean property. +- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY, + allowed step size is 0 to 3 +- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate time of MPHY + range is 1 to 9 +- ufs-pa-granularity : specifies Granularity for PA_TActivate and PA_Hibern8Time +- ufs-pa-tacctivate : specifies time to wake-up remote M-RX +- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state + +Note: If above properties are not defined it can be assumed that the supply +regulators or clocks are always on. + +Example: + ufshc@0x15570000 { + compatible = "samsung,exynos7-ufs"; + reg = <0x15570000 0x100>, + <0x15570100 0x100>, + <0x15571000 0x200>, + <0x15572000 0x300>; + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = <0 200 0>; + + vdd-hba-supply = <&xxx_reg0>; + vdd-hba-fixed-regulator; + vcc-supply = <&xxx_reg1>; + vcc-supply-1p8; + vccq-supply = <&xxx_reg2>; + vccq2-supply = <&xxx_reg3>; + vcc-max-microamp = 500000; + vccq-max-microamp = 200000; + vccq2-max-microamp = 200000; + + clocks = <&core 0>, <&ref 0>, <&iface 0>; + clock-names = "core", "sclk_unipro_main", "ref", "ref_parent"; + freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>; + + pclk-freq-avail-range = <70000000 133000000>; + + ufs,pwr-attr-mode = "FAST"; + ufs,pwr-attr-lane = /bits/ 8 <2>; + ufs,pwr-attr-gear = /bits/ 8 <2>; + ufs,pwr-attr-hs-series = "HS_rate_b"; + ufs,pwr-local-l2-timer = <8000 28000 20000>; + ufs,pwr-remote-l2-timer = <12000 32000 16000>; + ufs-rx-adv-fine-gran-sup_en = <1>; + ufs-rx-adv-fine-gran-step = <3>; + ufs-rx-adv-min-activate-time-cap = <9>; + ufs-pa-granularity = <6>; + ufs-pa-tacctivate = <6>; + ufs-pa-hibern8time = <20>; + };