From patchwork Sat Oct 10 09:55:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 528565 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id DA2FE1400CB for ; Sat, 10 Oct 2015 20:56:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751945AbbJJJ43 (ORCPT ); Sat, 10 Oct 2015 05:56:29 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:36120 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751460AbbJJJ4Z (ORCPT ); Sat, 10 Oct 2015 05:56:25 -0400 Received: by pablk4 with SMTP id lk4so109427651pab.3; Sat, 10 Oct 2015 02:56:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/Yjp7Y3nacFircstBHBY7JiccfiaRfawfaIKlhe+FJY=; b=ecE/bud8ubG/AfU322dgkta9uYQ48n0kCWqsI17VgOdD+nBDHXajK7NRGmXdDR5o7V ANG6LXAcVIyGRsxakjyBLdloSu8+yVhsBWjCuVSeO1Ulkd/dgiVnwPOpHQSfNqEX0ofw HK7MCqGCbF8ZtSyJK0QtojVLSCBz+sGsgqki2jYdpaOFu7+pV9u27/jEIDdeVVj9ViDS FurU2mIx8jjEpHsfVU1L4OoV2J4SJtzxpk9P1jU5zHuhSONbnrnZgzbUbkcBqVBG4QMf VpehVIvC7OpqtxHqTuwz3zPB8u5ZKAZlseWSfGI7bW5+yuez90Bt7M0CH1tF/5u36PQU Ql4w== X-Received: by 10.68.166.68 with SMTP id ze4mr21398779pbb.74.1444470985211; Sat, 10 Oct 2015 02:56:25 -0700 (PDT) Received: from localhost.localdomain ([192.253.240.50]) by smtp.gmail.com with ESMTPSA id wi10sm7235351pbc.31.2015.10.10.02.56.17 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 10 Oct 2015 02:56:24 -0700 (PDT) From: Chris Zhong To: heiko@sntech.de, linux-rockchip@lists.infradead.org Cc: Liu Ying , Liu Ying , Chris Zhong , devicetree@vger.kernel.org, Kumar Gala , linux-kernel@vger.kernel.org, Ian Campbell , Rob Herring , Pawel Moll , Mark Rutland Subject: [PATCH 04/10] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver Date: Sat, 10 Oct 2015 17:55:24 +0800 Message-Id: <1444470930-17150-5-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1444470930-17150-1-git-send-email-zyw@rock-chips.com> References: <1444470930-17150-1-git-send-email-zyw@rock-chips.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Liu Ying This patch adds device tree bindings for Synopsys DesignWare MIPI DSI host controller DRM bridge driver. Signed-off-by: Liu Ying Signed-off-by: Chris Zhong --- .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt diff --git a/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt new file mode 100644 index 0000000..bb87466 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt @@ -0,0 +1,76 @@ +Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller + +The controller is a digital core that implements all protocol functions +defined in the MIPI DSI specification, providing an interface between +the system and the MIPI DPHY, and allowing communication with a MIPI DSI +compliant display. + +Required properties: + - #address-cells: Should be <1>. + - #size-cells: Should be <0>. + - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi" + for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific + device tree binding documentations. A common compatible string + "snps,dw-mipi-dsi" should be appended for all SoCs. + - reg: Represent the physical address range of the controller. + - interrupts: Represent the controller's interrupt to the CPU(s). + - clocks, clock-names: Phandles to the controller's pll reference + clock(ref), configuration clock(cfg) and APB clock(pclk), as + described in [1]. + +For more required properties, please refer to relevant device tree binding +documentations which describe the controller embedded in specific SoCs. + +Required sub-nodes: + - A node to represent a DSI peripheral as described in [2]. + +For more required sub-nodes, please refer to relevant device tree binding +documentations which describe the controller embedded in specific SoCs. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt + +example: + gpr: iomuxc-gpr@020e0000 { + /* ... */ + }; + + mipi_dsi: mipi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_IPG>; + clock-names = "ref", "cfg", "pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_mipi>; + }; + }; + + port@1 { + reg = <1>; + + mipi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_mipi>; + }; + }; + }; + + panel { + compatible = "truly,tft480800-16-e-dsi"; + reg = <0>; + /* ... */ + }; + };