From patchwork Thu Oct 8 07:45:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Feng X-Patchwork-Id: 527627 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4902C14012C for ; Thu, 8 Oct 2015 19:07:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752443AbbJHIHF (ORCPT ); Thu, 8 Oct 2015 04:07:05 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:22668 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752054AbbJHIG6 (ORCPT ); Thu, 8 Oct 2015 04:06:58 -0400 Received: from 172.24.1.50 (EHLO szxeml428-hub.china.huawei.com) ([172.24.1.50]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BOO08838; Thu, 08 Oct 2015 15:46:04 +0800 (CST) Received: from u105-115.huawei.com (10.141.105.115) by szxeml428-hub.china.huawei.com (10.82.67.183) with Microsoft SMTP Server id 14.3.235.1; Thu, 8 Oct 2015 15:45:50 +0800 From: Chen Feng To: , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 1/3] docs: dts: Documentation for smmu in hi6220 SoC. Date: Thu, 8 Oct 2015 15:45:46 +0800 Message-ID: <1444290348-66509-1-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.141.105.115] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.5616235A.00F4, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 0b856e4f0c4332456c1a7ed5f1d06075 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Documentation for system mmu in hi6220 platform. Signed-off-by: Chen Feng Signed-off-by: Yu Dongbin --- .../bindings/iommu/hisi,hi6220-iommu.txt | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt diff --git a/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt new file mode 100644 index 0000000..32d1156 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt @@ -0,0 +1,52 @@ +Hi6220 SoC SMMU Device Driver devicetree document +======================================================================= +The Architecture of SMMU on Hi6220 SoC: + + +------------------------------------------------------------------+ + | | + | +---------+ +--------+ +-------------+ +-------+ | + | | ADE | | ISP | | V/J codec | | G3D | | + | +----|----+ +---|----+ +------|------+ +---|---| | + | | | | | | + | ---------v-----------v--------------v--------------v----- | + | Media Bus | + | --------------------------------|---------------|-------- | + | | | | + | +---v---------------v--------+ | + | | SMMU | | + | +----------|---------|-------+ | + | | | | + +--------------------------------------------|---------|-----------+ + | | + +------------v---------v-----------+ + | DDRC | + +----------------------------------+ + +Note: +The media system shared the same smmu IP. to access DDR memory. And all +media IP used the same page table. + +Below binding describes the system mmu for media system in hi6220 platform + +Required properties: +- compatible: Should be "hisilicon,hi6220-smmu" example: + compatible = "hisilicon,hi6220-smmu"; +- reg: A tuple of base address and size of System MMU registers. +- interrupts: An interrupt specifier for interrupt signal of System MMU. +- clocks: The clock used for smmu IP. +- clock-names: The name to enable clock with clock framework. +- #iommu-cells: The iommu-cells should be 1 for muti-master to use. + +Examples: + smmu@f4210000 { + compatible = "hisilicon,hi6220-smmu"; + reg = <0x0 0xf4210000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_MMU_CLK>, + <&media_ctrl HI6220_MED_MMU>, + <&sys_ctrl HI6220_MEDIA_PLL_SRC>; + clock-names = "smmu_clk", + "media_sc_clk", + "smmu_peri_clk"; + #iommu-cells = <1>; + };