From patchwork Wed Oct 7 09:14:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Liao X-Patchwork-Id: 527173 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 764F4140D72 for ; Wed, 7 Oct 2015 20:16:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752854AbbJGJQN (ORCPT ); Wed, 7 Oct 2015 05:16:13 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:55846 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752402AbbJGJQJ (ORCPT ); Wed, 7 Oct 2015 05:16:09 -0400 X-Listener-Flag: 11101 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 141740142; Wed, 07 Oct 2015 17:15:05 +0800 Received: from mtksdtcf04.mediatek.inc (10.21.12.144) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Wed, 7 Oct 2015 17:15:04 +0800 From: James Liao To: CC: Matthias Brugger , , Kevin Hilman , Daniel Kurtz , Sascha Hauer , , , , James Liao Subject: [PATCH v2 1/3] dt-bindings: soc: Add clocks for Mediatek SCPSYS unit Date: Wed, 7 Oct 2015 17:14:39 +0800 Message-ID: <1444209281-25536-2-git-send-email-jamesjj.liao@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444209281-25536-1-git-send-email-jamesjj.liao@mediatek.com> References: <1444209281-25536-1-git-send-email-jamesjj.liao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add clocks needed by Mediatek VENC and VENC_LT power domianis. These clocks were needed by accessing subsystem's registers, so they need to be enabled before power on these subsystems. Signed-off-by: James Liao --- Documentation/devicetree/bindings/soc/mediatek/scpsys.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index c051114..a6c8afc 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -17,9 +17,9 @@ Required properties: - reg: Address range of the SCPSYS unit - infracfg: must contain a phandle to the infracfg controller - clock, clock-names: clocks according to the common clock binding. - The clocks needed "mm" and "mfg". These are the - clocks which hardware needs to be enabled before - enabling certain power domains. + The clocks needed "mm", "mfg", "venc" and "venc_lt". + These are the clocks which hardware needs to be enabled + before enabling certain power domains. Example: @@ -30,7 +30,9 @@ Example: infracfg = <&infracfg>; clocks = <&clk26m>, <&topckgen CLK_TOP_MM_SEL>; - clock-names = "mfg", "mm"; + <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "mfg", "mm", "venc", "venc_lt"; }; Example consumer: