From patchwork Tue Oct 6 07:56:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel Fernandez X-Patchwork-Id: 526652 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C3923140D8E for ; Tue, 6 Oct 2015 18:57:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752401AbbJFH5c (ORCPT ); Tue, 6 Oct 2015 03:57:32 -0400 Received: from mail-wi0-f169.google.com ([209.85.212.169]:35878 "EHLO mail-wi0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752554AbbJFH5a (ORCPT ); Tue, 6 Oct 2015 03:57:30 -0400 Received: by wicgb1 with SMTP id gb1so152713639wic.1 for ; Tue, 06 Oct 2015 00:57:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=le/ZZrUETmc7p0vvx0uYndqgW2Lix9e24bO7Pydhjqw=; b=BN8zWOGOAbYNr2jv8p5bWPRAeob2xBx91IflvTqZppXr/R/1ZOM8DB+WqBD+VGwYG7 Oa8w6Q7PQGSQaNovtzUGNluCXEqSugC++HSIo1KhS24C14bvcUAPS18w++n97nAwgAeh 8u6m+khOH73kIcJG4Hc/t83BoR8eN3dysDWnzjHBIoFMNcJqH34tULpq+ZcUYj2l65jh O+LOuRwmtZSGm51w2sANt2cSdvWXnBvVKitjT7XhUHrxjlgzhTZWpN/j8ji/9Zwx19c9 /P3QnTQrldCLQ1To7Ta0hYFAYI6Xag2RQ88hbW5k22Gt3FdbWwF5VsMnXlwPDv8wPhp5 b2Qw== X-Gm-Message-State: ALoCoQk9pnegMNkDPp8/mP8lIzajBpiextTTZ162IrGoTau1a4e6mjO4NTtxEpVYeZoOb4Ckhl0D X-Received: by 10.194.77.77 with SMTP id q13mr40593729wjw.79.1444118248966; Tue, 06 Oct 2015 00:57:28 -0700 (PDT) Received: from lmenx315.lme.st.com (LPuteaux-656-1-48-212.w82-127.abo.wanadoo.fr. [82.127.83.212]) by smtp.gmail.com with ESMTPSA id s1sm18717083wik.16.2015.10.06.00.57.17 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Oct 2015 00:57:28 -0700 (PDT) From: Gabriel Fernandez To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , " David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Arnd Bergmann , Viresh Kumar , Thierry Reding , Phil Edworthy , Minghuan Lian , Tanmay Inamdar , , Sachin Kamat , Andrew Lunn , Liviu Dudau , Zhou Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, linux-pci@vger.kernel.org, Lee Jones Subject: [PATCH v5 2/3] PCI: st: Add Device Tree bindings for sti pcie Date: Tue, 6 Oct 2015 09:56:07 +0200 Message-Id: <1444118168-13086-3-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444118168-13086-1-git-send-email-gabriel.fernandez@linaro.org> References: <1444118168-13086-1-git-send-email-gabriel.fernandez@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier Signed-off-by: Gabriel Fernandez Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/st-pcie.txt | 56 +++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt b/Documentation/devicetree/bindings/pci/st-pcie.txt new file mode 100644 index 0000000..32e76d0 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt @@ -0,0 +1,56 @@ +STMicroelectronics STi PCIe controller + +This PCIe host controller is based on the Synopsis Designware PCIe IP +and thus inherits all the common properties defined in designware-pcie.txt. + +Required properties: + - compatible: Should be "st,pcie", "snps,dw-pcie" + + - reg: base address and length of the pcie controller, mem-window address + and length available to the controller. + + - interrupts: one GIC interrupt line connected to PCI MSI interrupt line + + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg + offset for IP configuration. + + - resets: phandle to the powerdown and reset controller for the PCIe IP. + See ../reset/reset.txt for details. + - reset-names: should be "powerdown" and "softreset". + + - phys: the phandle for the PHY device (used by generic PHY framework). + - phys-names: must be "pcie". + +Optional properties: + - reset-gpio: a GPIO spec to define which pin is connected to the bus reset. + +Example: + +pcie0: pcie@9b00000 { + compatible = "st,pcie", "snps,dw-pcie"; + device_type = "pci"; + reg = <0x09b00000 0x4000>, /* dbi cntrl registers */ + <0x2fff0000 0x00010000>, /* configuration space */ + <0x40000000 0x80000000>; /* lmi mem window */ + reg-names = "dbi", "config", "mem-window"; + st,syscfg = <&syscfg_core 0xd8 0xe0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x0FFF0000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT A */ + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT B */ + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT C */ + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT D */ + + resets = <&powerdown STIH407_PCIE0_POWERDOWN>, + <&softreset STIH407_PCIE0_SOFTRESET>; + reset-names = "powerdown", + "softreset"; + phys = <&phy_port0 PHY_TYPE_PCIE>; + phy-names = "pcie"; +};