From patchwork Mon Oct 5 23:41:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 526599 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 241EF140D7C for ; Tue, 6 Oct 2015 10:42:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750923AbbJEXmB (ORCPT ); Mon, 5 Oct 2015 19:42:01 -0400 Received: from avon.wwwdotorg.org ([70.85.31.133]:45227 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750780AbbJEXmA (ORCPT ); Mon, 5 Oct 2015 19:42:00 -0400 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id BC74A1E08F; Mon, 5 Oct 2015 17:41:59 -0600 (MDT) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 3724CE40CD; Mon, 5 Oct 2015 17:41:55 -0600 (MDT) From: Stephen Warren To: Thierry Reding , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Alexandre Courbot Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stephen Warren Subject: [PATCH 1/2] dt: update Tegra XUSB padctl binding for Tegra210 Date: Mon, 5 Oct 2015 17:41:56 -0600 Message-Id: <1444088517-31615-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.98.6 at avon.wwwdotorg.org X-Virus-Status: Clean Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Stephen Warren Tegra210 introduces some new options for pad muxing. Document these in the XUSB padctl binding. Be more explicit about the valid values for the compatible property, and in particular point out that Tegra210 isn't fully backwards-compatible with Tegra124, since some registers have moved about. Signed-off-by: Stephen Warren --- .../pinctrl/nvidia,tegra124-xusb-padctl.txt | 34 +++++++++++++++------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt index 30676ded85bb..3952d893635c 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt @@ -13,9 +13,12 @@ how to describe and reference PHYs in device trees. Required properties: -------------------- -- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl". - Otherwise, must contain '"nvidia,-xusb-padctl", - "nvidia-tegra124-xusb-padctl"', where is tegra132 or tegra210. +- compatible: Valid options are: + Tegra124: "nvidia,tegra124-xusb-padctl". + Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia-tegra124-xusb-padctl". + Tegra210: "nvidia-tegra210-xusb-padctl". + Note that Tegra210 is not backwards-compatible with Tegra124 due to some + registers having been moved. - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. @@ -45,18 +48,21 @@ Unspecified is represented as an absent property, and off/on are represented as integer values 0 and 1. Required properties: -- nvidia,lanes: An array of strings. Each string is the name of a lane. +- nvidia,lanes: An array of strings. Each string is the name of a lane (pad). + Valid values for lanes are listed below. Optional properties: -- nvidia,function: A string that is the name of the function (pad) that the - pin or group should be assigned to. Valid values for function names are - listed below. +- nvidia,function: A string that is the name of the function (IO controller) + that the pin or group should be assigned to. Valid values for function names + are listed below. - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes) Note that not all of these properties are valid for all lanes. Lanes can be divided into three groups: - - otg-0, otg-1, otg-2: + - otg-0, otg-1, otg-2, otg-3, usb2-bias: + + (otg-3, usb2-bias are valid on Tegra210 only.) Valid functions for this group are: "snps", "xusb", "uart", "rsvd". @@ -64,13 +70,21 @@ divided into three groups: - ulpi-0, hsic-0, hsic-1: + (ulpi-0 is valid on Tegra124 and Tegra132 only.) + Valid functions for this group are: "snps", "xusb". The nvidia,iddq property does not apply to this group. - - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0: + - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6, sata-0: + + (pcie-5, pcie-6 are valid on Tegra210 only.) + + On Tegra124, Tegra132, valid functions for this group are: "pcie", "usb3", + "sata", "rsvd". - Valid functions for this group are: "pcie", "usb3", "sata", "rsvd". + On Tegra210, valid functions for this group are "pcie-x1", "usb3", + "sata", "pcie-x4". Example: