From patchwork Tue Sep 22 14:12:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 521071 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 0DD081401AF for ; Wed, 23 Sep 2015 00:18:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756763AbbIVORw (ORCPT ); Tue, 22 Sep 2015 10:17:52 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:2727 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757982AbbIVOQw (ORCPT ); Tue, 22 Sep 2015 10:16:52 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.15.0.59/8.15.0.59) with SMTP id t8MEFg1c020472; Tue, 22 Sep 2015 07:16:22 -0700 Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 1x177e84u7-1 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 22 Sep 2015 07:16:22 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 22 Sep 2015 07:16:20 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server id 15.0.1044.25 via Frontend Transport; Tue, 22 Sep 2015 07:16:20 -0700 Received: from xhacker.marvell.com (unknown [10.37.135.134]) by maili.marvell.com (Postfix) with ESMTP id 6FA483F703F; Tue, 22 Sep 2015 07:16:18 -0700 (PDT) From: Jisheng Zhang To: , , , , , , , CC: , , , , Jisheng Zhang Subject: [PATCH 4/5] dt-bindings: add binding for marvell berlin4ct SoC Date: Tue, 22 Sep 2015 22:12:35 +0800 Message-ID: <1442931156-5877-5-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: <1442931156-5877-1-git-send-email-jszhang@marvell.com> References: <1442931156-5877-1-git-send-email-jszhang@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2015-09-22_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1509220208 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a dt-binding include for Marvell berlin4ct clock IDs. Signed-off-by: Jisheng Zhang --- .../bindings/clock/marvell,berlin4ct.txt | 38 +++++++++++++++ include/dt-bindings/clock/berlin4ct.h | 56 ++++++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt create mode 100644 include/dt-bindings/clock/berlin4ct.h diff --git a/Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt b/Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt new file mode 100644 index 0000000..a489473 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,berlin4ct.txt @@ -0,0 +1,38 @@ +* Marvell berlin4ct Clock Controllers + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +The berlin4ct clock subsystem generates and supplies clock to various +controllers within the berlin4ct SoC. The berlin4ct contains 3 clock controller +blocks: pll, gateclk, berlin-clk. + +Required Properties: + +- compatible: should be one of the following. + - "marvell,berlin-pll" - pll compatible + - "marvell,berlin4ct-clk" - berlin clk compatible + - "marvell,berlin4ct-gateclk" - gateclk compatible +- reg: physical base address of the clock controller and length of memory mapped + region. For pll, the second reg defines the bypass register base address and + length of memory mapped region. +- #clock-cells: for pll should 0, for gateclk and berlin clk should be 1. +- #bypass-shift: the bypass bit in bypass register. + +Example: + +syspll: syspll { + compatible = "marvell,berlin-pll"; + reg = <0xea0200 0x14>, <0xea0710 4>; + #clock-cells = <0>; + clocks = <&osc>; + bypass-shift = /bits/ 8 <0>; +}; + +clk: clk { + compatible = "marvell,berlin4ct-clk"; + reg = <0xea0720 0x144>; + #clock-cells = <1>; + clocks = <&syspll>; +}; diff --git a/include/dt-bindings/clock/berlin4ct.h b/include/dt-bindings/clock/berlin4ct.h new file mode 100644 index 0000000..f742f6b --- /dev/null +++ b/include/dt-bindings/clock/berlin4ct.h @@ -0,0 +1,56 @@ +/* + * Berlin2 BG2Q clock tree IDs + */ + +/* GATE CLK */ +#define GATECLK_TSPSYS 0 +#define GATECLK_USB0CORE 1 +#define GATECLK_ZSPSYS 2 +#define GATECLK_SDIOSYS 3 +#define GATECLK_ETHCORE 4 +#define GATECLK_PCIE0SYS 5 +#define GATECLK_SATA0CORE 6 +#define GATECLK_NFCSYS 7 +#define GATECLK_EMMCSYS 8 +#define GATECLK_IHB0SYS 9 + +/* BERLIN CLK */ +#define CLK_CPUFASTREF 0 +#define CLK_MEMFASTREF 1 +#define CLK_CFG 2 +#define CLK_PERIFSYS 3 +#define CLK_HB 4 +#define CLK_ATB 5 +#define CLK_DECODER 6 +#define CLK_DECODERM3 7 +#define CLK_DECODERPCUBE 8 +#define CLK_ENCODER 9 +#define CLK_OVPCORE 10 +#define CLK_GFX2DCORE 11 +#define CLK_GFX3DCORE 12 +#define CLK_GFX3DSH 13 +#define CLK_GFX3DSYS 14 +#define CLK_GFX2DSYS 15 +#define CLK_AVIOSYS 16 +#define CLK_VPPSYS 17 +#define CLK_EDDC 18 +#define CLK_AVIOBIU 19 +#define CLK_ZSP 20 +#define CLK_TSP 21 +#define CLK_TSPREF 22 +#define CLK_NDS 23 +#define CLK_NOCS 24 +#define CLK_APBCORE 25 +#define CLK_EMMC 26 +#define CLK_SD0 27 +#define CLK_SD1 28 +#define CLK_DLLMSTREF 29 +#define CLK_GETHRGMII 30 +#define CLK_GETHRGMIISYS 31 +#define CLK_USIM0 32 +#define CLK_PCIETEST 33 +#define CLK_USB2TEST 34 +#define CLK_USB3TEST 35 +#define CLK_USB3CORE 36 +#define CLK_NFCECC 37 +#define CLK_BCM 38