From patchwork Fri Sep 11 14:14:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 516822 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 938A8140082 for ; Sat, 12 Sep 2015 00:17:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753391AbbIKORl (ORCPT ); Fri, 11 Sep 2015 10:17:41 -0400 Received: from mail-wi0-f174.google.com ([209.85.212.174]:37902 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752702AbbIKOOi (ORCPT ); Fri, 11 Sep 2015 10:14:38 -0400 Received: by wiclk2 with SMTP id lk2so60005789wic.1 for ; Fri, 11 Sep 2015 07:14:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pDVRSGa5umVCy0jPs+GgwNZSZARCosInJttGVxXf2e8=; b=X2s1nL45ppnpXmHuwB+611aT4YSOcKRHCtjtfxilbIAU8Txg96Zfr5miB0k2U+CVA7 VZdny4CFrdRGkpkdw1tso4x1jlqLgmYS5OJZvjRfNE6SMYuxsbScGYGltG+N7BFqnTWT BlHva+am6m9XVLfPP+fOq6e1CtqZUHugSq3afKoez9AZX1K4zmk2DxxThOmiR41iShZj 8MVjjUo9jXH9xWvKwZ9FN2OrI9+0d3MzhQjQslNESttS+yZaDnIX/VKvHs/1A20ywrsL 4ktMx4nnIQoIqSYm+viJ5im8m4xcuPNyTSa7xv22UD+eomSMAKsBVic0qG17HV2wW/Ua 5tiA== X-Gm-Message-State: ALoCoQk4fYPzZqOgkTkSGcTB5JLdggTjAo0g/Dq5F70TDq8XHDl23vtVesu2f6/9o4M+ropdWMI0 X-Received: by 10.180.108.177 with SMTP id hl17mr17249466wib.45.1441980877580; Fri, 11 Sep 2015 07:14:37 -0700 (PDT) Received: from localhost.localdomain (cpc14-aztw22-2-0-cust189.18-1.cable.virginm.net. [82.45.1.190]) by smtp.gmail.com with ESMTPSA id i6sm577236wje.33.2015.09.11.07.14.36 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 Sep 2015 07:14:36 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, srinivas.kandagatla@gmail.com, maxime.coquelin@st.com, patrice.chotard@st.com, vinod.koul@intel.com Cc: peter.griffin@linaro.org, lee.jones@linaro.org, robh+dt@kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, Ludovic Barre Subject: [PATCH v2 1/9] dmaengine: st_fdma: Add STMicroelectronics FDMA DT binding documentation Date: Fri, 11 Sep 2015 15:14:23 +0100 Message-Id: <1441980871-24475-2-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441980871-24475-1-git-send-email-peter.griffin@linaro.org> References: <1441980871-24475-1-git-send-email-peter.griffin@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the DT binding documentation for the FDMA constroller found on STi based chipsets from STMicroelectronics. Signed-off-by: Ludovic Barre Signed-off-by: Peter Griffin --- Documentation/devicetree/bindings/dma/st_fdma.txt | 78 +++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/st_fdma.txt diff --git a/Documentation/devicetree/bindings/dma/st_fdma.txt b/Documentation/devicetree/bindings/dma/st_fdma.txt new file mode 100644 index 0000000..c24b8d7 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/st_fdma.txt @@ -0,0 +1,78 @@ +* STMicroelectronics Flexible Direct Memory Access Device Tree bindings + +The FDMA is a general-purpose direct memory access controller capable of +supporting 16 independent DMA channels. It accepts up to 32 DMA requests. +The FDMA is based on a Slim processor which require a firmware. + +* FDMA Controller + +Required properties: +- compatible : Should be "st,stih407-fdma-mpe31" +- reg : Should contain DMA registers location and length +- interrupts : Should contain one interrupt shared by all channels +- dma-channels : Number of channels supported by the controller +- #dma-cells : Must be <3>. See DMA client section below +- st,fdma-id : Must contain fdma controller number +- clocks : Must contain an entry for each name in clock-names +- clock-names : Must contain "fdma_slim, fdma_hi, fdma_low, fdma_ic" entries +See: Documentation/devicetree/bindings/clock/clock-bindings.txt + + +Example: + + fdma1: fdma-app@8e40000 { + compatible = "st,stih407-fdma-mpe31"; + reg = <0x8e40000 0x20000>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + st,fdma-id = <0>; + clocks = <&CLK_S_C0_FLEXGEN CLK_FDMA>, + <&CLK_S_C0_FLEXGEN CLK_TX_ICN_DMU>, + <&CLK_S_C0_FLEXGEN CLK_TX_ICN_DMU>, + <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>; + clock-names = "fdma_slim", + "fdma_hi", + "fdma_low", + "fdma_ic"; + }; + +* DMA client + +Required properties: +- dmas: Comma separated list of dma channel requests +- dma-names: Names of the aforementioned requested channels + +Each dmas request consists of 4 cells: +1. A phandle pointing to the FDMA controller +2. The request line number +3. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h) + -bit 2-0: Holdoff value, dreq will be masked for + 0x0: 0-0.5us + 0x1: 0.5-1us + 0x2: 1-1.5us + -bit 17: data swap + 0x0: disabled + 0x1: enabled + -bit 21: Increment Address + 0x0: no address increment between transfers + 0x1: increment address between transfers + -bit 22: 2 STBus Initiator Coprocessor interface + 0x0: high priority port + 0x1: low priority port +4. transfers type + 0 free running + 1 paced + +Example: + + snd_uni_player2: snd-uni-player@2 { + compatible = "st,snd_uni_player"; + status = "okay"; + reg = <0x8D82000 0x158>; + interrupts = ; + version = <5>; + dmas = <&fdma0 4 0 1>; + dma-names = "tx"; + description = "Uni Player #2 (DAC)"; + };