diff mbox

[v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2

Message ID 1436888777-29742-1-git-send-email-claudiu.manoil@freescale.com
State Needs Review / ACK, archived
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Commit Message

Claudiu Manoil July 14, 2015, 3:46 p.m. UTC
This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.

Signed-off-by: Alison Wang <alison.wang@freescale.com>

Enable support for the second interrupt group register block
and the corresponding Rx/Tx/Err interrupt sources, for each
eTSEC node.  DT binding documentation updates.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2:
 - register block size is 0x1000 (4kB memory page), not 0x8000;
 - reg property has 2 "address" and resp. 2 "size" cells;
 - remove optional/ obsoleted properties;
 - use register block address as queue-group id for consistency;
 - binding documentation updates for missing vendor properties;


 .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-
 arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
 arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
 arch/arm/boot/dts/ls1021a.dtsi                     | 92 ++++++++++++++++++++++
 4 files changed, 137 insertions(+), 1 deletion(-)

Comments

Fabio Estevam July 14, 2015, 3:57 p.m. UTC | #1
On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
<claudiu.manoil@freescale.com> wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
>
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node.  DT binding documentation updates.
>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>

It seems you missed to put Alison in the From field.

You should also put his Signed-off-by tag just before yours.
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Fabio Estevam July 14, 2015, 4:17 p.m. UTC | #2
On Tue, Jul 14, 2015 at 1:13 PM, Manoil Claudiu
<claudiu.manoil@freescale.com> wrote:

>> You should also put his Signed-off-by tag just before yours.
>
> Is this a rule invented by you?  Last time I checked this was a

No, just usual practice.
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Shawn Guo July 27, 2015, 2:28 p.m. UTC | #3
On Tue, Jul 14, 2015 at 06:46:17PM +0300, Claudiu Manoil wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
> 
> Signed-off-by: Alison Wang <alison.wang@freescale.com>

SoBs should be put together.

> 
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node.  DT binding documentation updates.
> 
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>

Please use "ARM: dts: ls1021a: ..." as subject prefix.

> ---
> v2:
>  - register block size is 0x1000 (4kB memory page), not 0x8000;
>  - reg property has 2 "address" and resp. 2 "size" cells;
>  - remove optional/ obsoleted properties;
>  - use register block address as queue-group id for consistency;
>  - binding documentation updates for missing vendor properties;
> 
> 
>  .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-

Bindings doc should be a separate patch reviewed by device tree
maintainers.

>  arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
>  arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
>  arch/arm/boot/dts/ls1021a.dtsi                     | 92 ++++++++++++++++++++++

Please separate soc level dts changes from board level changes.

>  4 files changed, 137 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> index 1e97532..b3291c7 100644
> --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> @@ -45,7 +45,7 @@ Properties:
>  
>    - device_type : Should be "network"
>    - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
> -  - compatible : Should be "gianfar"
> +  - compatible : "gianfar", "fsl-etsec2"

You meant "fsl,etsec2", which is what I see from dts changes?

>    - reg : Offset and length of the register set for the device
>    - interrupts : For FEC devices, the first interrupt is the device's
>      interrupt.  For TSEC and eTSEC devices, the first interrupt is
> @@ -57,6 +57,10 @@ Properties:
>      "rgmii-id", as all other connection types are detected by hardware.
>    - fsl,magic-packet : If present, indicates that the hardware supports
>      waking up via magic packet.
> +  - fsl,wake-on-filer: Indicates that the device can wake up the system
> +    by generating a filer interrupt. Depending on the wake-on-lan mode
> +    set for this device, the filer interrupt can be triggered by certain
> +    user-defined ethernet packets (usually ARP or L2 unicast packets).
>    - bd-stash : If present, indicates that the hardware supports stashing
>      buffer descriptors in the L2.
>    - rx-stash-len : Denotes the number of bytes of a received buffer to stash
> diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
> index 9c5e16b..f16a061 100644
> --- a/arch/arm/boot/dts/ls1021a-qds.dts
> +++ b/arch/arm/boot/dts/ls1021a-qds.dts
> @@ -75,6 +75,26 @@
>  	};
>  };
>  
> +&enet0 {
> +	tbi-handle = <&tbi0>;

tbi-handle is undocumented.

> +	phy-handle = <&sgmii_phy1c>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet1 {
> +	tbi-handle = <&tbi0>;
> +	phy-handle = <&sgmii_phy1d>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet2 {
> +	phy-handle = <&rgmii_phy3>;
> +	phy-connection-type = "rgmii-id";
> +	status = "okay";
> +};
> +
>  &i2c0 {
>  	status = "okay";
>  
> diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
> index a2c591e..4b61766 100644
> --- a/arch/arm/boot/dts/ls1021a-twr.dts
> +++ b/arch/arm/boot/dts/ls1021a-twr.dts
> @@ -73,6 +73,26 @@
>  	};
>  };
>  
> +&enet0 {
> +	tbi-handle = <&tbi1>;
> +	phy-handle = <&sgmii_phy2>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet1 {
> +	tbi-handle = <&tbi1>;
> +	phy-handle = <&sgmii_phy0>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet2 {
> +	phy-handle = <&rgmii_phy1>;
> +	phy-connection-type = "rgmii-id";
> +	status = "okay";
> +};
> +
>  &i2c0 {
>  	status = "okay";
>  };
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index c70bb27..cc48d56 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
>  		serial3 = &lpuart3;
>  		serial4 = &lpuart4;
>  		serial5 = &lpuart5;
> +		ethernet0 = &enet0;
> +		ethernet1 = &enet1;
> +		ethernet2 = &enet2;
>  		sysclk = &sysclk;
>  	};
>  
> @@ -391,6 +394,95 @@
>  			reg = <0x0 0x2d24000 0x0 0x4000>;
>  		};
>  
> +		enet0: ethernet@2d10000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,magic-packet;
> +			fsl,wake-on-filer;
> +			local-mac-address = [ 00 00 00 00 00 00 ];

What is this all zero local-mac-address used for?

Shawn

> +			ranges;
> +
> +			queue-group@2d10000 {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d10000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d14000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d14000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet1: ethernet@2d50000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group@2d50000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d50000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d54000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d54000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet2: ethernet@2d90000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			ranges;
> +
> +			queue-group@2d90000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d90000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			queue-group@2d94000  {
> +				#address-cells = <2>;
> +				#size-cells = <2>;
> +				reg = <0x0 0x2d94000 0x0 0x1000>;
> +				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>  		usb@8600000 {
>  			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
>  			reg = <0x0 0x8600000 0x0 0x1000>;
> -- 
> 1.7.11.7
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
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Claudiu Manoil July 27, 2015, 4:09 p.m. UTC | #4
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Monday, July 27, 2015 5:28 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; shawn.guo@linaro.org; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
> 
[...]
> >
> >  .../devicetree/bindings/net/fsl-tsec-phy.txt       |  6 +-
> 
> Bindings doc should be a separate patch reviewed by device tree
> maintainers.
> 
> >  arch/arm/boot/dts/ls1021a-qds.dts                  | 20 +++++
> >  arch/arm/boot/dts/ls1021a-twr.dts                  | 20 +++++
> >  arch/arm/boot/dts/ls1021a.dtsi                     | 92
> ++++++++++++++++++++++
> 
> Please separate soc level dts changes from board level changes.
> 

Ok, will break this in 3 patches (soc, boards, bindings), trimmed down as much as possible,
with remaining findings addressed.  Thanks.
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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..b3291c7 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,7 +45,7 @@  Properties:
 
   - device_type : Should be "network"
   - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
-  - compatible : Should be "gianfar"
+  - compatible : "gianfar", "fsl-etsec2"
   - reg : Offset and length of the register set for the device
   - interrupts : For FEC devices, the first interrupt is the device's
     interrupt.  For TSEC and eTSEC devices, the first interrupt is
@@ -57,6 +57,10 @@  Properties:
     "rgmii-id", as all other connection types are detected by hardware.
   - fsl,magic-packet : If present, indicates that the hardware supports
     waking up via magic packet.
+  - fsl,wake-on-filer: Indicates that the device can wake up the system
+    by generating a filer interrupt. Depending on the wake-on-lan mode
+    set for this device, the filer interrupt can be triggered by certain
+    user-defined ethernet packets (usually ARP or L2 unicast packets).
   - bd-stash : If present, indicates that the hardware supports stashing
     buffer descriptors in the L2.
   - rx-stash-len : Denotes the number of bytes of a received buffer to stash
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@ 
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@ 
 	};
 };
 
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..cc48d56 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@ 
 		serial3 = &lpuart3;
 		serial4 = &lpuart4;
 		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
 		sysclk = &sysclk;
 	};
 
@@ -391,6 +394,95 @@ 
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		enet0: ethernet@2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,magic-packet;
+			fsl,wake-on-filer;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@2d10000 {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d10000 0x0 0x1000>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d14000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d14000 0x0 0x1000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet1: ethernet@2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@2d50000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d50000 0x0 0x1000>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d54000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d54000 0x0 0x1000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet2: ethernet@2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			ranges;
+
+			queue-group@2d90000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d90000 0x0 0x1000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			queue-group@2d94000  {
+				#address-cells = <2>;
+				#size-cells = <2>;
+				reg = <0x0 0x2d94000 0x0 0x1000>;
+				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		usb@8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;