From patchwork Wed Jun 10 16:44:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gary Bisson X-Patchwork-Id: 482801 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E6D8314029D for ; Thu, 11 Jun 2015 02:44:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751003AbbFJQoY (ORCPT ); Wed, 10 Jun 2015 12:44:24 -0400 Received: from mail-wg0-f51.google.com ([74.125.82.51]:33296 "EHLO mail-wg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966348AbbFJQoM (ORCPT ); Wed, 10 Jun 2015 12:44:12 -0400 Received: by wgez8 with SMTP id z8so40188308wge.0 for ; Wed, 10 Jun 2015 09:44:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=H1YKR2SvBsuhQTKGH6rIVYJ11FvR4yru08qFLqUY4B4=; b=FrHGT89sVgRzc3KDuxIgKzXcclCsUsG+f5BSTjlWosT8EL0SJJDnSvdSVzIM79HE2J R9F5sHklVC9r5MorBPKvUxVAOgPc8jJNRsUWUo8V+4X+O9Gs7PtPHnBZuq9CRQGPPyLU oMLz09oPLMp9m6g6Z3ZdVCWMiXoPhz0gNBuEsYfCbeR6RlK5MUWdb9VS/pZFqB89T3Pj yQ/52eTR5ZwNSOGtWMVVO3RUxBTQ2Nd3VGFkxLMtFxgkWVfB1scLwaGvkcMSKq/UiNAh 5jjsG/Gh/OwB5c9DgaZfTt448npfYK7ppgtsuVe2G9jEbi2azqe9mKAEG8ZGDqTNuC5d 8eOw== X-Gm-Message-State: ALoCoQkBByohxidHjIPp4OIrSW0x/W04AQVWcTIz0peuFJ8qFKxoaP1ZXKSBmg8MDuSZc96hplqw X-Received: by 10.180.198.166 with SMTP id jd6mr20229192wic.48.1433954651108; Wed, 10 Jun 2015 09:44:11 -0700 (PDT) Received: from t450s.lan (89-92-157-132.hfc.dyn.abo.bbox.fr. [89.92.157.132]) by mx.google.com with ESMTPSA id hn7sm15331967wjc.16.2015.06.10.09.44.09 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Jun 2015 09:44:10 -0700 (PDT) From: Gary Bisson To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, p.zabel@pengutronix.de, airlied@linux.ie, thierry.reding@gmail.com, eric.nelson@boundarydevices.com, Gary Bisson Subject: [PATCH v3 2/2] drm/panel: Add display timing for Okaya RS800480T-7X0GP Date: Wed, 10 Jun 2015 18:44:23 +0200 Message-Id: <1433954663-31444-3-git-send-email-gary.bisson@boundarydevices.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1433954663-31444-1-git-send-email-gary.bisson@boundarydevices.com> References: <1432827466-8104-1-git-send-email-gary.bisson@boundarydevices.com> <1433954663-31444-1-git-send-email-gary.bisson@boundarydevices.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the Okaya RS800480T-7X0GP to the DRM simple panel driver. The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel LCD interface. It supports pixel clocks in the range of 30-40 MHz. This panel details can be found at: http://boundarydevices.com/product/7-800x480-display/ Signed-off-by: Gary Bisson --- .../bindings/panel/okaya,rs800480t_7x0gp.txt | 7 +++++ drivers/gpu/drm/panel/panel-simple.c | 33 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt diff --git a/Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt b/Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt new file mode 100644 index 0000000..f7c729d --- /dev/null +++ b/Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt @@ -0,0 +1,7 @@ +OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel + +Required properties: +- compatible: should be "okaya,rs800480t_7x0gp" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index f94201b..5262be1 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -943,6 +943,36 @@ static const struct panel_desc lg_lp129qe = { }, }; +static const struct display_timing okaya_rs800480t_7x0gp_timing = { + .pixelclock = { 30000000, 30000000, 40000000 }, + .hactive = { 800, 800, 800 }, + .hfront_porch = { 40, 40, 40 }, + .hback_porch = { 40, 40, 40 }, + .hsync_len = { 1, 48, 48 }, + .vactive = { 480, 480, 480 }, + .vfront_porch = { 13, 13, 13 }, + .vback_porch = { 29, 29, 29 }, + .vsync_len = { 3, 3, 3 }, + .flags = DISPLAY_FLAGS_DE_HIGH, +}; + +static const struct panel_desc okaya_rs800480t_7x0gp = { + .timings = &okaya_rs800480t_7x0gp_timing, + .num_timings = 1, + .bpc = 6, + .size = { + .width = 154, + .height = 87, + }, + .delay = { + .prepare = 41, + .enable = 50, + .unprepare = 41, + .disable = 50, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, +}; + static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { .clock = 25000, .hdisplay = 480, @@ -1113,6 +1143,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "lg,lp129qe", .data = &lg_lp129qe, }, { + .compatible = "okaya,rs800480t_7x0gp", + .data = &okaya_rs800480t_7x0gp, + }, { .compatible = "ortustech,com43h4m85ulc", .data = &ortustech_com43h4m85ulc, }, {