From patchwork Tue May 26 19:27:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Olivari X-Patchwork-Id: 476709 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B08181402A2 for ; Wed, 27 May 2015 05:28:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751428AbbEZT2K (ORCPT ); Tue, 26 May 2015 15:28:10 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56369 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751781AbbEZT12 (ORCPT ); Tue, 26 May 2015 15:27:28 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 5AFD8141ABA; Tue, 26 May 2015 19:27:27 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 45DD6141ABD; Tue, 26 May 2015 19:27:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-caf-smtp.dmz.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.3.1 Received: from mathieu-linux.qualcomm.com (qf-scl1nat.qualcomm.com [207.114.132.30]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mathieu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 764C5141ABC; Tue, 26 May 2015 19:27:26 +0000 (UTC) From: Mathieu Olivari To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, mturquette@linaro.org, sboyd@codeaurora.org, peppe.cavallaro@st.com, mathieu@codeaurora.org, agross@codeaurora.org, joshc@codeaurora.org, architt@codeaurora.org, georgi.djakov@linaro.org, wsa@the-dreams.de, rnayak@codeaurora.org, davem@davemloft.net, vbridger@opensource.altera.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH 5/5] net: stmmac: ipq806x: document device tree bindings Date: Tue, 26 May 2015 12:27:17 -0700 Message-Id: <1432668437-27763-6-git-send-email-mathieu@codeaurora.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1432668437-27763-1-git-send-email-mathieu@codeaurora.org> References: <1432668437-27763-1-git-send-email-mathieu@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree bindings documentation for the QCA IPQ806x variant of the Synopsys DesignWare MAC. Signed-off-by: Mathieu Olivari --- .../devicetree/bindings/net/ipq806x-dwmac.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt diff --git a/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt new file mode 100644 index 0000000..6d7ab4e --- /dev/null +++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt @@ -0,0 +1,35 @@ +* IPQ806x DWMAC Ethernet controller + +The device inherits all the properties of the dwmac/stmmac devices +described in the file net/stmmac.txt with the following changes. + +Required properties: + +- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac" + and any applicable more detailed version number + described in net/stmmac.txt + +- qcom,nss-common: should contain a phandle to a syscon device mapping the + nss-common registers. + +- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the + qsgmii-csr registers. + +Example: + + gmac: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37000000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE1_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE1_RESET>; + reset-names = "stmmaceth"; + };