From patchwork Fri May 22 21:03:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 475802 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5695E14027F for ; Sat, 23 May 2015 07:05:44 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Wvm8/POp; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757254AbbEVVEA (ORCPT ); Fri, 22 May 2015 17:04:00 -0400 Received: from mail-wg0-f41.google.com ([74.125.82.41]:36021 "EHLO mail-wg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757448AbbEVVD6 (ORCPT ); Fri, 22 May 2015 17:03:58 -0400 Received: by wgbgq6 with SMTP id gq6so28220151wgb.3; Fri, 22 May 2015 14:03:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eU9Pbpy5UcNtF5zwqgl5kV/wA+B1v2uKLg9oq5t/psA=; b=Wvm8/POpwOPYv1ZX1ResoQA9FnpRXxi+OqSoEPL1stjTYLTl9AA0NJpDebJAD1aGJh aamIR1KUO69Ot+MfdRCpHxQZzTBuB7MXIarjf+v2dHQQeXZB0CO2504V8osU6NjuQzQN /sPxSr9lTqBzh5yFZ40Y8Eqx9JQQDhbEvnBED3WJA40Z2FoP4HJsoygwcBjLF3y0tvY/ KZkZGZWniWE/BQEdHbTpHLpQNOwFtg+Pfn2wRa6fzEeDe2tDrR65+nL4gSCuylYs8USR XE5zpjlV3pgGyPLREnwZ0KmP2HP/IJawpxH5bXj2jkQVOa768fcCgecGjobIkYnWmhsG Rp8g== X-Received: by 10.194.61.133 with SMTP id p5mr18834778wjr.132.1432328636479; Fri, 22 May 2015 14:03:56 -0700 (PDT) Received: from lmecul0520.st.com. (224.72.140.88.rev.sfr.net. [88.140.72.224]) by mx.google.com with ESMTPSA id bh7sm4857915wjb.8.2015.05.22.14.03.53 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 May 2015 14:03:55 -0700 (PDT) From: Maxime Coquelin To: Arnd Bergmann , Greg Kroah-Hartman , Daniel Lezcano , Daniel Thompson , Kamil Lulko , u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Thomas Gleixner , Jiri Slaby , Maxime Coquelin , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, linux-api@vger.kernel.org Subject: [PATCH v9 1/5] dt-bindings: Document the STM32 timer bindings Date: Fri, 22 May 2015 23:03:32 +0200 Message-Id: <1432328616-16964-2-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432328616-16964-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1432328616-16964-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds documentation of device tree bindings for the STM32 timer. Tested-by: Chanwoo Choi Acked-by: Rob Herring Signed-off-by: Maxime Coquelin --- .../devicetree/bindings/timer/st,stm32-timer.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/st,stm32-timer.txt diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.txt b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt new file mode 100644 index 0000000..8ef28e7 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt @@ -0,0 +1,22 @@ +. STMicroelectronics STM32 timer + +The STM32 MCUs family has several general-purpose 16 and 32 bits timers. + +Required properties: +- compatible : Should be "st,stm32-timer" +- reg : Address and length of the register set +- clocks : Reference on the timer input clock +- interrupts : Reference to the timer interrupt + +Optional properties: +- resets: Reference to a reset controller asserting the timer + +Example: + +timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + resets = <&rrc 259>; + clocks = <&clk_pmtr1>; +};