From patchwork Thu May 7 17:35:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 469771 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 0B07714030D for ; Fri, 8 May 2015 04:44:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751332AbbEGSoZ (ORCPT ); Thu, 7 May 2015 14:44:25 -0400 Received: from mail-by2on0108.outbound.protection.outlook.com ([207.46.100.108]:51167 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751174AbbEGSoY (ORCPT ); Thu, 7 May 2015 14:44:24 -0400 Received: from BN3PR0301CA0033.namprd03.prod.outlook.com (10.160.180.171) by CY1PR03MB1358.namprd03.prod.outlook.com (10.163.16.24) with Microsoft SMTP Server (TLS) id 15.1.154.19; Thu, 7 May 2015 18:44:23 +0000 Received: from BN1AFFO11FD032.protection.gbl (2a01:111:f400:7c10::166) by BN3PR0301CA0033.outlook.office365.com (2a01:111:e400:4000::43) with Microsoft SMTP Server (TLS) id 15.1.160.16 via Frontend Transport; Thu, 7 May 2015 18:44:23 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD032.mail.protection.outlook.com (10.58.52.186) with Microsoft SMTP Server (TLS) id 15.1.160.8 via Frontend Transport; Thu, 7 May 2015 18:44:22 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t47IiFvk020705; Thu, 7 May 2015 11:44:19 -0700 From: To: , , CC: , , Frank Li Subject: [PATCH V8 1/6] Document: dt: binding: imx: update document for imx7d support Date: Fri, 8 May 2015 01:35:53 +0800 Message-ID: <1431020158-13789-2-git-send-email-Frank.Li@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431020158-13789-1-git-send-email-Frank.Li@freescale.com> References: <1431020158-13789-1-git-send-email-Frank.Li@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(189002)(199003)(46102003)(92566002)(2950100001)(229853001)(47776003)(36756003)(50466002)(189998001)(86152002)(48376002)(105606002)(107886002)(5001960100002)(5001920100001)(50986999)(87936001)(77156002)(62966003)(77096005)(76176999)(6806004)(104016003)(19580395003)(5001770100001)(50226001)(85426001)(19580405001)(86362001)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR03MB1358; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR03MB1358; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:CY1PR03MB1358; BCL:0; PCL:0; RULEID:; SRVR:CY1PR03MB1358; X-Forefront-PRVS: 056929CBB8 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2015 18:44:22.6132 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR03MB1358 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Frank Li This part just add necessary change to boot imx7d. Update clock, pinctrl and gpt for imx7d Signed-off-by: Frank Li --- .../devicetree/bindings/clock/imx7d-clock.txt | 13 +++++++++++ .../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 27 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx7d-clock.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt diff --git a/Documentation/devicetree/bindings/clock/imx7d-clock.txt b/Documentation/devicetree/bindings/clock/imx7d-clock.txt new file mode 100644 index 0000000..9d3026d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx7d-clock.txt @@ -0,0 +1,13 @@ +* Clock bindings for Freescale i.MX7 Dual + +Required properties: +- compatible: Should be "fsl,imx7d-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names: should include entries "ckil", "osc" + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h +for the full list of i.MX7 Dual clock IDs. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt new file mode 100644 index 0000000..8bbf25d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt @@ -0,0 +1,27 @@ +* Freescale i.MX7 Dual IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx7d-iomuxc" +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual + Reference Manual for detailed CONFIG settings. + +CONFIG bits definition: +PAD_CTL_PUS_100K_DOWN (0 << 5) +PAD_CTL_PUS_5K_UP (1 << 5) +PAD_CTL_PUS_47K_UP (2 << 5) +PAD_CTL_PUS_100K_UP (3 << 5) +PAD_CTL_PUE (1 << 4) +PAD_CTL_HYS (1 << 3) +PAD_CTL_SRE_SLOW (1 << 2) +PAD_CTL_SRE_FAST (0 << 2) +PAD_CTL_DSE_X1 (0 << 0) +PAD_CTL_DSE_X2 (1 << 0) +PAD_CTL_DSE_X3 (2 << 0) +PAD_CTL_DSE_X4 (3 << 0)