From patchwork Wed Apr 29 14:20:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 466087 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id DC1BB140320 for ; Thu, 30 Apr 2015 00:23:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423009AbbD2OXi (ORCPT ); Wed, 29 Apr 2015 10:23:38 -0400 Received: from mail-bn1on0146.outbound.protection.outlook.com ([157.56.110.146]:52317 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1422999AbbD2OXh (ORCPT ); Wed, 29 Apr 2015 10:23:37 -0400 Received: from DM2PR03CA0047.namprd03.prod.outlook.com (10.141.96.46) by CY1PR03MB1357.namprd03.prod.outlook.com (25.163.16.23) with Microsoft SMTP Server (TLS) id 15.1.148.16; Wed, 29 Apr 2015 14:23:34 +0000 Received: from BN1BFFO11FD036.protection.gbl (2a01:111:f400:7c10::1:199) by DM2PR03CA0047.outlook.office365.com (2a01:111:e400:2428::46) with Microsoft SMTP Server (TLS) id 15.1.148.16 via Frontend Transport; Wed, 29 Apr 2015 14:23:34 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD036.mail.protection.outlook.com (10.58.144.99) with Microsoft SMTP Server (TLS) id 15.1.154.14 via Frontend Transport; Wed, 29 Apr 2015 14:23:34 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t3TENL6W015727; Wed, 29 Apr 2015 07:23:31 -0700 From: To: , , , CC: , , , Frank Li Subject: [PATCH V7 03/10] Document: dt: binding: imx: update document for imx7d support Date: Wed, 29 Apr 2015 22:20:03 +0800 Message-ID: <1430317210-18333-4-git-send-email-Frank.Li@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430317210-18333-1-git-send-email-Frank.Li@freescale.com> References: <1430317210-18333-1-git-send-email-Frank.Li@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(199003)(189002)(47776003)(19580405001)(2201001)(50226001)(46102003)(48376002)(50986999)(76176999)(6806004)(2950100001)(86152002)(87936001)(104016003)(92566002)(19580395003)(5001770100001)(36756003)(50466002)(105606002)(229853001)(62966003)(106466001)(86362001)(77156002)(77096005)(85426001)(5001960100001)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR03MB1357; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR03MB1357; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:CY1PR03MB1357; BCL:0; PCL:0; RULEID:; SRVR:CY1PR03MB1357; X-Forefront-PRVS: 05610E64EE X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2015 14:23:34.1560 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR03MB1357 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Frank Li This part just add necessary change to boot imx7d. Update clock, pinctrl and gpt for imx7d Signed-off-by: Frank Li --- .../devicetree/bindings/clock/imx7d-clock.txt | 13 +++++++++++ .../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 27 ++++++++++++++++++++++ .../devicetree/bindings/timer/fsl,imxgpt.txt | 3 +++ 3 files changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx7d-clock.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt diff --git a/Documentation/devicetree/bindings/clock/imx7d-clock.txt b/Documentation/devicetree/bindings/clock/imx7d-clock.txt new file mode 100644 index 0000000..3db0076 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx7d-clock.txt @@ -0,0 +1,13 @@ +* Clock bindings for Freescale i.MX7 Dual + +Required properties: +- compatible: Should be "fsl,imx7d-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h +for the full list of i.MX7 Dual clock IDs. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt new file mode 100644 index 0000000..3c9d8ed --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt @@ -0,0 +1,27 @@ +* Freescale i.MX7 Dual IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx7d-iomuxc" +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + imx6sx-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual + Reference Manual for detailed CONFIG settings. + +CONFIG bits definition: +PAD_CTL_PUS_100K_DOWN (0 << 5) +PAD_CTL_PUS_5K_UP (1 << 5) +PAD_CTL_PUS_47K_UP (2 << 5) +PAD_CTL_PUS_100K_UP (3 << 5) +PAD_CTL_PUE (1 << 4) +PAD_CTL_HYS (1 << 3) +PAD_CTL_SRE_SLOW (1 << 2) +PAD_CTL_SRE_FAST (0 << 2) +PAD_CTL_DSE_X1 (0 << 0) +PAD_CTL_DSE_X2 (1 << 0) +PAD_CTL_DSE_X3 (2 << 0) +PAD_CTL_DSE_X4 (3 << 0) diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt index 9809b11..c14843b 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt @@ -7,6 +7,9 @@ Required properties: - interrupts : A list of 4 interrupts; one per timer channel. - clocks : The clocks provided by the SoC to drive the timer. +Supported : + imx1,imx27,imx51,imx53,imx6q,imx6dl,imx6sl,imx6sx,imx7d. + Example: gpt1: timer@10003000 {