From patchwork Thu Mar 26 11:15:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hyungwon Hwang X-Patchwork-Id: 454952 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 195B41400B7 for ; Thu, 26 Mar 2015 22:16:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751402AbbCZLP7 (ORCPT ); Thu, 26 Mar 2015 07:15:59 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:25917 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752484AbbCZLP6 (ORCPT ); Thu, 26 Mar 2015 07:15:58 -0400 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NLT0078VGMFOYC0@mailout3.samsung.com> for devicetree@vger.kernel.org; Thu, 26 Mar 2015 20:15:51 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.115]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 26.7E.17016.76AE3155; Thu, 26 Mar 2015 20:15:51 +0900 (KST) X-AuditID: cbfee68d-f79296d000004278-95-5513ea67b70a Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 0D.B8.20081.66AE3155; Thu, 26 Mar 2015 20:15:51 +0900 (KST) Received: from localhost.localdomain ([10.252.82.145]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NLT00A2SGMAMQ10@mmp2.samsung.com>; Thu, 26 Mar 2015 20:15:50 +0900 (KST) From: Hyungwon Hwang To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, inki.dae@samsung.com, daniel@fooishbar.org Cc: sw0312.kim@samsung.com, jy0922.shim@samsung.com, dh09.lee@samsung.com, cw00.choi@samsung.com, Hyungwon Hwang Subject: [PATCH v3 6/8] drm/exynos: dsi: add support for Exynos5433 Date: Thu, 26 Mar 2015 20:15:38 +0900 Message-id: <1427368540-28010-7-git-send-email-human.hwang@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1427368540-28010-1-git-send-email-human.hwang@samsung.com> References: <1427368540-28010-1-git-send-email-human.hwang@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRmVeSWpSXmKPExsWyRsSkWDf9lXCowZdT/BbXvzxntbjSOp3V Yv6Rc6wW18/bWVz5+p7NYumMPlaLSfcnsFi8uHeRxWLG5JdsDpweL75uY/a4332cyaNvyypG j8+b5AJYorhsUlJzMstSi/TtErgyFi44zFTQaFLR8fYfSwPjEe0uRk4OCQETifOPepghbDGJ C/fWs3UxcnEICSxllGib8IEJpujN5RVMEInpjBLde/qhqn4wSvS++8cGUsUmoCex4NoPdhBb RCBXov/FC7AOZoEeRonGK5NZQBLCAs4SN+8uBhvLIqAqsXvBU0YQm1fAXWJNy1KodXISJ49N ZgWxOQU8JHrmPAaLCwHVnO3exQwyVEJgHrvE2gU/GSEGCUh8m3wIaAEHUEJWYtMBqH8kJQ6u uMEygVF4ASPDKkbR1ILkguKk9CJDveLE3OLSvHS95PzcTYzAkD/971nvDsbbB6wPMQpwMCrx 8P7oFw4VYk0sK67MPcRoCrRhIrOUaHI+MLLySuINjc2MLExNTI2NzC3NlMR5FaV+BgsJpCeW pGanphakFsUXleakFh9iZOLglGpgDMrrXj3zpd6WvZ2Wm/MMd75b4rDy+DuPx493P5m/InFT cZbps6XTe+6yZuYsnSLIFbLq0CK/RZlXKpy57wtIBRiU79U8VjPhrKf9su6pb3Y+1WAUsntz 7HVTC9+bKbn7s29pVfal5uxn+brv9vSXFvxhk93vbCmU6T229gn75O+vF///5KB+tliJpTgj 0VCLuag4EQC3xiyydAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrNIsWRmVeSWpSXmKPExsVy+t9jQd30V8KhBhPes1hc//Kc1eJK63RW i/lHzrFaXD9vZ3Hl63s2i6Uz+lgtJt2fwGLx4t5FFosZk1+yOXB6vPi6jdnjfvdxJo++LasY PT5vkgtgiWpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLxCdB1 y8wBukVJoSwxpxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmLFwwWGmgkaTio63 /1gaGI9odzFyckgImEi8ubyCCcIWk7hwbz1bFyMXh5DAdEaJ7j39UM4PRoned//YQKrYBPQk Flz7wQ5iiwjkSvS/eMEEUsQs0MMo0XhlMgtIQljAWeLm3cVgY1kEVCV2L3jKCGLzCrhLrGlZ CrVOTuLkscmsIDangIdEz5zHYHEhoJqz3buYJzDyLmBkWMUomlqQXFCclJ5rqFecmFtcmpeu l5yfu4kRHFHPpHYwrmywOMQowMGoxMP7o184VIg1say4MvcQowQHs5IIr98ToBBvSmJlVWpR fnxRaU5q8SFGU6CrJjJLiSbnA6M9ryTe0NjEzMjSyNzQwsjYXEmcV8m+LURIID2xJDU7NbUg tQimj4mDU6qBkde9Y0Ozzxn+NTNvCpy7cnuFmwGP7m83GTmdizz5Pc8L/ym2/Fb4XLBYwUts 2uFpNe82acR03lzWa7Pk8pYTi6yEKm6E8csG5qiGlvyq6U/Ms2F95DTROWW10sFtmy9LfDGa dWQ7Y+2h2kWaB3pfmLXVub1f4vb6VyhXg6HKpdmTHG8p9iiKK7EUZyQaajEXFScCAAGx2Km+ AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds support for Exynos5433 mipi dsi. Signed-off-by: Hyungwon Hwang --- Changes for v2: - change the author of "drm/exynos: dsi: add support for Exynos5433 SoC" to Hyungwon Hwang by the previous author's will Changes for v3: - Separated from the patch "drm/exynos: dsi: add support for Exynos5433 SoC" in version 2. - use defines for more readable code - fix typos .../devicetree/bindings/video/exynos_dsim.txt | 1 + drivers/gpu/drm/exynos/Kconfig | 2 +- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 69 +++++++++++++++++++++- 3 files changed, 68 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index 39940ca..8b12bfe 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt @@ -6,6 +6,7 @@ Required properties: "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */ "samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */ "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */ + "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */ - reg: physical base address and length of the registers set for the device - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index f78f3ef..e873502 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -47,7 +47,7 @@ config DRM_EXYNOS_DPI config DRM_EXYNOS_DSI bool "EXYNOS DRM MIPI-DSI driver support" - depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON) + depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS5433_DECON || DRM_EXYNOS7_DECON) select DRM_MIPI_DSI select DRM_PANEL default n diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 2d9a249..d1ecd0f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -131,6 +131,7 @@ #define DSIM_INT_PLL_STABLE (1 << 31) #define DSIM_INT_SW_RST_RELEASE (1 << 30) #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) +#define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) #define DSIM_INT_BTA (1 << 25) #define DSIM_INT_FRAME_DONE (1 << 24) #define DSIM_INT_RX_TIMEOUT (1 << 21) @@ -179,6 +180,8 @@ /* DSIM_PHYCTRL */ #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) +#define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) +#define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) /* DSIM_PHYTIMING */ #define DSIM_PHYTIMING_LPX(x) ((x) << 8) @@ -206,7 +209,9 @@ #define DSI_WRITE(dsi, reg, val) writel((val), REG((dsi), (reg))) #define DSI_READ(dsi, reg) readl(REG((dsi), (reg))) -static char *clk_names[2] = { "bus_clk", "sclk_mipi" }; +static char *clk_names[5] = { "bus_clk", "sclk_mipi", + "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", + "sclk_rgb_vclk_to_dsim0" }; enum exynos_dsi_transfer_type { EXYNOS_DSI_TX, @@ -335,6 +340,30 @@ static unsigned int regs[] = { [DSIM_PHYTIMING2_REG] = 0x6c, }; +static unsigned int exynos5433_regs[] = { + [DSIM_STATUS_REG] = 0x04, + [DSIM_SWRST_REG] = 0x0C, + [DSIM_CLKCTRL_REG] = 0x10, + [DSIM_TIMEOUT_REG] = 0x14, + [DSIM_CONFIG_REG] = 0x18, + [DSIM_ESCMODE_REG] = 0x1C, + [DSIM_MDRESOL_REG] = 0x20, + [DSIM_MVPORCH_REG] = 0x24, + [DSIM_MHPORCH_REG] = 0x28, + [DSIM_MSYNC_REG] = 0x2C, + [DSIM_INTSRC_REG] = 0x34, + [DSIM_INTMSK_REG] = 0x38, + [DSIM_PKTHDR_REG] = 0x3C, + [DSIM_PAYLOAD_REG] = 0x40, + [DSIM_RXFIFO_REG] = 0x44, + [DSIM_FIFOCTRL_REG] = 0x4C, + [DSIM_PLLCTRL_REG] = 0x94, + [DSIM_PHYCTRL_REG] = 0xA4, + [DSIM_PHYTIMING_REG] = 0xB4, + [DSIM_PHYTIMING1_REG] = 0xB8, + [DSIM_PHYTIMING2_REG] = 0xBC, +}; + enum values { RESET_TYPE, PLL_TIMER, @@ -371,6 +400,24 @@ static unsigned int values[] = { [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), }; +static unsigned int exynos5433_values[] = { + [RESET_TYPE] = DSIM_FUNCRST, + [PLL_TIMER] = 22200, + [STOP_STATE_CNT] = 0xa, + [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), + [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, + [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, + [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), + [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), + [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), + [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), + [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), + [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), + [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), + [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), + [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), +}; + static struct exynos_dsi_driver_data exynos3_dsi_driver_data = { .regs = regs, .plltmr_reg = 0x50, @@ -416,6 +463,17 @@ static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { .values = values, }; +static struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { + .regs = exynos5433_regs, + .plltmr_reg = 0xa0, + .has_clklane_stop = 1, + .num_clks = 5, + .max_freq = 1500, + .wait_for_reset = 0, + .num_bits_resol = 12, + .values = exynos5433_values, +}; + static struct of_device_id exynos_dsi_of_match[] = { { .compatible = "samsung,exynos3250-mipi-dsi", .data = &exynos3_dsi_driver_data }, @@ -425,6 +483,8 @@ static struct of_device_id exynos_dsi_of_match[] = { .data = &exynos4415_dsi_driver_data }, { .compatible = "samsung,exynos5410-mipi-dsi", .data = &exynos5_dsi_driver_data }, + { .compatible = "samsung,exynos5433-mipi-dsi", + .data = &exynos5433_dsi_driver_data }, { } }; @@ -1182,13 +1242,16 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) DSI_WRITE(dsi, DSIM_INTSRC_REG, status); if (status & DSIM_INT_SW_RST_RELEASE) { - u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY); + u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | + DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE | + DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE); DSI_WRITE(dsi, DSIM_INTMSK_REG, mask); complete(&dsi->completed); return IRQ_HANDLED; } - if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY))) + if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | + DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE))) return IRQ_HANDLED; if (exynos_dsi_transfer_finish(dsi))