From patchwork Wed Mar 25 23:03:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Barry Song <21cnbao@gmail.com> X-Patchwork-Id: 454818 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 07A721400D5 for ; Thu, 26 Mar 2015 10:05:24 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=NssI94L5; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751500AbbCYXFW (ORCPT ); Wed, 25 Mar 2015 19:05:22 -0400 Received: from mail-wg0-f54.google.com ([74.125.82.54]:34406 "EHLO mail-wg0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751227AbbCYXFW (ORCPT ); Wed, 25 Mar 2015 19:05:22 -0400 Received: by wgs2 with SMTP id 2so45074040wgs.1; Wed, 25 Mar 2015 16:05:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=oVuSxNO3KD+WDJFjmB6Yzk5hYhlNQKixSw0Dqh3Z+tA=; b=NssI94L5E6dfXWMwW4RnRhFVDbyQlgDeCuq7/Qb3n+Giju4n5FtGFfgmDFTgtDElCW HwKq6n70aXi/etK+t2vPwCMuMVJayA0k90EM2jXfM41UOZWLmXo+3EyH0yEnUAH0cSWg mxurgsBZUwbDTwcw4Fi3nlX9bg65AhxQqpWoq2xw68UVlUrTbXcCon+ExrSgDTengsR2 f2QI8j9QMXnPwuS6WtVIizWyWn/XGEo+jJYbxd3Z2FgblIUj8fTMc1pE+Nghgy2T2Ef5 s2WYHXxK14f0dGN3CbHIIzaxqPBNQWlX9DnOh+CrAH8icBrd0mOcmyRv9jsIyYJLF877 LevA== X-Received: by 10.180.89.34 with SMTP id bl2mr42718460wib.23.1427324720678; Wed, 25 Mar 2015 16:05:20 -0700 (PDT) Received: from localhost.localdomain (p549987CB.dip0.t-ipconnect.de. [84.153.135.203]) by mx.google.com with ESMTPSA id q10sm5696136wjr.41.2015.03.25.16.05.18 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Mar 2015 16:05:19 -0700 (PDT) From: Barry Song <21cnbao@gmail.com> To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org, ohad@wizery.com Cc: linux-kernel@vger.kernel.org, Wei Chen , Barry Song Subject: [PATCH v2 RESEND] drivers: hwspinlock: add CSR atlas7 implementation Date: Thu, 26 Mar 2015 07:03:05 +0800 Message-Id: <1427324585-3936-1-git-send-email-21cnbao@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Wei Chen Add hwspinlock support for the CSR atlas7 SoC. The Hardware Spinlock device on atlas7 provides hardware assistance for synchronization between the multiple processors in the system (dual Cortex-A7, CAN bus Cortex-M3 and audio DSP). Signed-off-by: Wei Chen Signed-off-by: Barry Song --- .../bindings/hwspinlock/sirf,hwspinlock.txt | 18 +++ drivers/hwspinlock/Kconfig | 12 ++ drivers/hwspinlock/Makefile | 1 + drivers/hwspinlock/sirf_hwspinlock.c | 151 +++++++++++++++++++++ 4 files changed, 182 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwspinlock/sirf,hwspinlock.txt create mode 100644 drivers/hwspinlock/sirf_hwspinlock.c diff --git a/Documentation/devicetree/bindings/hwspinlock/sirf,hwspinlock.txt b/Documentation/devicetree/bindings/hwspinlock/sirf,hwspinlock.txt new file mode 100644 index 0000000..b22c492 --- /dev/null +++ b/Documentation/devicetree/bindings/hwspinlock/sirf,hwspinlock.txt @@ -0,0 +1,18 @@ +SIRF Hardware spinlock device Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "sirf,hwspinlock" + +- reg : the register address of hwspinlock + +- num-spinlocks : how many spinlocks this device provides + +Example: + hwspinlock { + compatible = "sirf,hwspinlock"; + reg = <0x13240000 0x00010000>; + + num-spinlocks = <30>; + }; diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig index 3612cb5..fc400e4 100644 --- a/drivers/hwspinlock/Kconfig +++ b/drivers/hwspinlock/Kconfig @@ -29,4 +29,16 @@ config HSEM_U8500 If unsure, say N. +config HWSPINLOCK_SIRF + tristate "SIRF Hardware Spinlock device" + depends on ARCH_SIRF + select HWSPINLOCK + help + Say y here to support the SIRF Hardware Spinlock device, which + provides a synchronisation mechanism for the various processor + on the SoC. + + It's safe to say n here if you're not interested in SIRF hardware + spinlock or just want a bare minimum kernel. + endmenu diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile index 93eb64b..472b82d 100644 --- a/drivers/hwspinlock/Makefile +++ b/drivers/hwspinlock/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o +obj-$(CONFIG_HWSPINLOCK_SIRF) += sirf_hwspinlock.o diff --git a/drivers/hwspinlock/sirf_hwspinlock.c b/drivers/hwspinlock/sirf_hwspinlock.c new file mode 100644 index 0000000..b68722a --- /dev/null +++ b/drivers/hwspinlock/sirf_hwspinlock.c @@ -0,0 +1,151 @@ +/* + * SIRF hardware spinlock driver + * + * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hwspinlock_internal.h" + +struct sirf_hwspinlock { + void __iomem *io_base; + struct hwspinlock_device bank; +}; + +/* Hardware spinlock register offsets */ +#define HW_SPINLOCK_RD_DEBUG 0x400 +#define HW_SPINLOCK_BASE 0x404 +#define HW_SPINLOCK_OFFSET(x) (HW_SPINLOCK_BASE + 0x4 * (x)) + +/* Possible values of HW_SPINLOCK_REG */ +#define HW_SPINLOCK_LOCKED 0 +#define HW_SPINLOCK_FREE 1 + +static int sirf_hwspinlock_trylock(struct hwspinlock *lock) +{ + void __iomem *lock_addr = lock->priv; + + /* attempt to acquire the lock by reading its value */ + return (HW_SPINLOCK_FREE == readl(lock_addr)); +} + +static void sirf_hwspinlock_unlock(struct hwspinlock *lock) +{ + void __iomem *lock_addr = lock->priv; + + /* release the lock by writing 0 to it */ + writel(HW_SPINLOCK_LOCKED, lock_addr); +} + +static void sirf_hwspinlock_relax(struct hwspinlock *lock) +{ + ndelay(50); +} + +static const struct hwspinlock_ops sirf_hwspinlock_ops = { + .trylock = sirf_hwspinlock_trylock, + .unlock = sirf_hwspinlock_unlock, + .relax = sirf_hwspinlock_relax, +}; + +static int sirf_hwspinlock_probe(struct platform_device *pdev) +{ + struct sirf_hwspinlock *hwspin; + struct hwspinlock *hwlock; + u32 num_of_locks; + int idx, ret; + + ret = of_property_read_u32(pdev->dev.of_node, + "num-spinlocks", &num_of_locks); + if (ret) { + dev_err(&pdev->dev, + "Unable to find hwspinlock number. ret=%d\n", ret); + return -ENODEV; + } + + hwspin = devm_kzalloc(&pdev->dev, sizeof(*hwspin) + + sizeof(*hwlock) * num_of_locks, GFP_KERNEL); + if (!hwspin) + return -ENOMEM; + + /* retrieve io base */ + hwspin->io_base = of_iomap(pdev->dev.of_node, 0); + if (!hwspin->io_base) + ret = -ENOMEM; + + for (idx = 0; idx < num_of_locks; idx++) { + hwlock = &hwspin->bank.lock[idx]; + hwlock->priv = hwspin->io_base + HW_SPINLOCK_OFFSET(idx); + } + + platform_set_drvdata(pdev, hwspin); + + pm_runtime_enable(&pdev->dev); + + ret = hwspin_lock_register(&hwspin->bank, &pdev->dev, + &sirf_hwspinlock_ops, 0, num_of_locks); + if (ret) + goto reg_failed; + + return 0; + +reg_failed: + pm_runtime_disable(&pdev->dev); + iounmap(hwspin->io_base); + + return ret; +} + +static int sirf_hwspinlock_remove(struct platform_device *pdev) +{ + struct sirf_hwspinlock *hwspin = platform_get_drvdata(pdev); + int ret; + + ret = hwspin_lock_unregister(&hwspin->bank); + if (ret) { + dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); + return ret; + } + + pm_runtime_disable(&pdev->dev); + + iounmap(hwspin->io_base); + + return 0; +} + +static const struct of_device_id sirf_hwpinlock_ids[] = { + { .compatible = "sirf,hwspinlock", }, + {}, +}; +MODULE_DEVICE_TABLE(of, sirf_hwpinlock_ids); + +static struct platform_driver sirf_hwspinlock_driver = { + .probe = sirf_hwspinlock_probe, + .remove = sirf_hwspinlock_remove, + .driver = { + .name = "atlas7_hwspinlock", + .of_match_table = of_match_ptr(sirf_hwpinlock_ids), + }, +}; + +module_platform_driver(sirf_hwspinlock_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("SIRF Hardware spinlock driver"); +MODULE_AUTHOR("Wei Chen ");