From patchwork Thu Feb 26 09:34:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Christophe PLAGNIOL-VILLARD X-Patchwork-Id: 443880 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8104B1400B6 for ; Thu, 26 Feb 2015 20:49:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753392AbbBZJtE (ORCPT ); Thu, 26 Feb 2015 04:49:04 -0500 Received: from 3.mo69.mail-out.ovh.net ([188.165.52.203]:42339 "EHLO 3.mo69.mail-out.ovh.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753215AbbBZJtB (ORCPT ); Thu, 26 Feb 2015 04:49:01 -0500 X-Greylist: delayed 9293 seconds by postgrey-1.27 at vger.kernel.org; Thu, 26 Feb 2015 04:49:01 EST Received: from mail409.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo69.mail-out.ovh.net (Postfix) with SMTP id 5FE45FFBB2B for ; Thu, 26 Feb 2015 10:41:36 +0100 (CET) Received: from b0.ovh.net (HELO queueout) (213.186.33.50) by b0.ovh.net with SMTP; 26 Feb 2015 11:35:33 +0200 Received: from ns203013.ovh.net (HELO localhost) (plagnioj%jcrosoft.com@91.121.171.124) by ns0.ovh.net with SMTP; 26 Feb 2015 11:35:25 +0200 From: Jean-Christophe PLAGNIOL-VILLARD To: linux-arm-kernel@lists.infradead.org Cc: Jean-Christophe PLAGNIOL-VILLARD , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH] pinctrl: dt: at91: new binding Date: Thu, 26 Feb 2015 10:34:54 +0100 Message-Id: <1424943294-8805-1-git-send-email-plagnioj@jcrosoft.com> X-Mailer: git-send-email 2.1.3 X-Ovh-Tracer-Id: 16779567787467516925 X-Ovh-Remote: 91.121.171.124 (ns203013.ovh.net) X-Ovh-Local: 213.186.33.20 (ns0.ovh.net) X-OVH-SPAMSTATE: OK X-OVH-SPAMSCORE: -100 X-OVH-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeejledrvdejucetufdoteggodetrfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeejledrvdejucetufdoteggodetrfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Today if we want to disable a pio bank we may will siliently break pinctrl configuration in the DT. This will be detected only at runtime. So move the pinctrl configuration to the bank instead of the bus. This allow to detect pinctrl issue at DT compiling time when disable a bank. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Cc: Linus Walleij Cc: devicetree@vger.kernel.org --- .../bindings/pinctrl/atmel,at91-pinctrl.txt | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index b7a93e8..78355ee 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -148,3 +148,69 @@ dbgu: serial@fffff200 { pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; }; + +II) New Bindings per PIO Block + +This allow to detect pinctrl issue at DT compiling time when disable a bank + +Required properties for iomux controller: +- compatible: "atmel,at91rm9200-pio-pinctrl" or "atmel,at91sam9x5-pio-pinctrl" + or "atmel,sama5d3-pio-pinctrl" +- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be + configured in this periph mode. All the periph and bank need to be describe. + +How to create such array: + +Each column will represent the possible peripheral of the pinctrl for the bank + +Take an example on the 9260 +Peripheral: 2 ( A and B) +=> + + /* A B */ + 0xffffffff 0xffc00c3b /* pioA */ + +For each peripheral/bank we will descibe in a u32 if a pin can be +configured in it by putting 1 to the pin bit (1 << pin) + +Required properties for pin configuration node: +- atmel,pins: 3 integers array, represents a group of pins mux and config + setting. The format is atmel,pins = . + The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... + +Bits used for CONFIG: +cf atmel,at91-pinctrl + +pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio", "atmel,at91rm9200-pio-pinctrl"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + + /* A B */ + atmel,mux-mask = <0xffffffff 0x7fff3ccf>; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <14 0x1 0x0 /* PB14 periph A */ + 15 0x1 0x1>; /* PB15 periph A with pullup */ + }; + }; +}; + +dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 4 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + status = "disabled"; +}; + +if you have to use multiple bank + pinctrl-0 = <&pinctrl_ip_piaa>, <&pinctrl_ip_piab>;