From patchwork Thu Feb 12 06:01:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 439076 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 0F80D140129 for ; Thu, 12 Feb 2015 16:59:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755156AbbBLF6P (ORCPT ); Thu, 12 Feb 2015 00:58:15 -0500 Received: from mail-bl2on0109.outbound.protection.outlook.com ([65.55.169.109]:55712 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755080AbbBLF6M (ORCPT ); Thu, 12 Feb 2015 00:58:12 -0500 Received: from CH1PR03CA011.namprd03.prod.outlook.com (10.255.156.156) by DM2PR0301MB0640.namprd03.prod.outlook.com (25.160.96.14) with Microsoft SMTP Server (TLS) id 15.1.87.13; Thu, 12 Feb 2015 05:58:10 +0000 Received: from BN1AFFO11FD055.protection.gbl (10.255.156.132) by CH1PR03CA011.outlook.office365.com (10.255.156.156) with Microsoft SMTP Server (TLS) id 15.1.87.18 via Frontend Transport; Thu, 12 Feb 2015 05:58:09 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD055.mail.protection.outlook.com (10.58.53.70) with Microsoft SMTP Server (TLS) id 15.1.87.10 via Frontend Transport; Thu, 12 Feb 2015 05:58:09 +0000 Received: from victor.ap.freescale.net (victor.ap.freescale.net [10.192.241.62]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t1C5v5tU031246; Wed, 11 Feb 2015 22:58:04 -0700 From: Liu Ying To: CC: , , , , , , , , , , , , , Subject: [PATCH RFC v9 12/20] Documentation: dt-bindings: Add bindings for i.MX specific Synopsys DW MIPI DSI driver Date: Thu, 12 Feb 2015 14:01:35 +0800 Message-ID: <1423720903-24806-13-git-send-email-Ying.Liu@freescale.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1423720903-24806-1-git-send-email-Ying.Liu@freescale.com> References: <1423720903-24806-1-git-send-email-Ying.Liu@freescale.com> X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Ying.Liu@freescale.com; vger.kernel.org; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(62966003)(48376002)(77156002)(50466002)(87936001)(36756003)(19580395003)(46102003)(19580405001)(110136001)(2351001)(229853001)(92566002)(85426001)(6806004)(105606002)(106466001)(104016003)(86362001)(2950100001)(50226001)(47776003)(77096005)(50986999)(76176999)(217873001); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB0640; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0640; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004); SRVR:DM2PR0301MB0640; X-Forefront-PRVS: 0485417665 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:; SRVR:DM2PR0301MB0640; X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2015 05:58:09.8779 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0301MB0640 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds device tree bindings for i.MX specific Synopsys DW MIPI DSI driver. Signed-off-by: Liu Ying --- v8->v9: * Rebase onto the imx-drm/next branch of Philipp Zabel's open git repository. * To address Philipp's comment, mention that a common compatible string "snps,dw-mipi-dsi" should be appended. * To address Philipp's comment, add a new required clock pclk and clean up clock-names. v7->v8: * None. v6->v7: * None. v5->v6: * Add the #address-cells and #size-cells properties in the example 'ports' node. * Remove the useless pllref_gate clock from the required clocks, clock-names property. v4->v5: * None. v3->v4: * Newly introduced in v4. This is separated from the relevant driver patch in v3 to address Stefan Wahren's comment. .../devicetree/bindings/drm/imx/mipi_dsi.txt | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt diff --git a/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt new file mode 100644 index 0000000..4bd8451 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/imx/mipi_dsi.txt @@ -0,0 +1,81 @@ +i.MX specific Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller + +MIPI DSI host controller +======================== + +The MIPI DSI host controller is a Synopsys DesignWare IP. +The common device tree documentation for this controller can be found +at [1]. + +Required properties: + - #address-cells: Should be <1>. + - #size-cells: Should be <0>. + - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi" + for i.MX6q/sdl SoCs. And, a common compatible string "snps,dw-mipi-dsi" + should be appended. + - reg: Physical base address of the controller and length of memory + mapped region. + - interrupts: The controller's interrupt number to the CPU(s). + - gpr: Should be <&gpr>. + The phandle points to the iomuxc-gpr region containing the + multiplexer control register for the controller. + - clocks, clock-names: Phandles to the controller's pll reference + clock(ref), configuration clock(cfg) and APB clock(pclk), as described + in [2] and [3]. + +Required sub-nodes: + - ports: This node may contain up to four port nodes with endpoint + definitions as defined in [4], corresponding to the four inputs to + the controller multiplexer. + - A node to represent a DSI peripheral as described in [5]. + +[1] Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt. +[2] Documentation/devicetree/bindings/clock/clock-bindings.txt +[3] Documentation/devicetree/bindings/clock/imx6q-clock.txt +[4] Documentation/devicetree/bindings/media/video-interfaces.txt +[5] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt + +example: + gpr: iomuxc-gpr@020e0000 { + /* ... */ + }; + + mipi_dsi: mipi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_IPG>; + clock-names = "ref", "cfg", "pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_mipi>; + }; + }; + + port@1 { + reg = <1>; + + mipi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_mipi>; + }; + }; + }; + + panel { + compatible = "truly,tft480800-16-e-dsi"; + reg = <0>; + /* ... */ + }; + };