From patchwork Thu Dec 4 21:56:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 417928 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id DF5E61400D5 for ; Fri, 5 Dec 2014 08:55:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933224AbaLDVyZ (ORCPT ); Thu, 4 Dec 2014 16:54:25 -0500 Received: from mail-gw3-out.broadcom.com ([216.31.210.64]:14923 "EHLO mail-gw3-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932717AbaLDVyX (ORCPT ); Thu, 4 Dec 2014 16:54:23 -0500 X-IronPort-AV: E=Sophos;i="5.07,518,1413270000"; d="scan'208";a="52155331" Received: from irvexchcas06.broadcom.com (HELO IRVEXCHCAS06.corp.ad.broadcom.com) ([10.9.208.53]) by mail-gw3-out.broadcom.com with ESMTP; 04 Dec 2014 14:03:51 -0800 Received: from IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) by IRVEXCHCAS06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server (TLS) id 14.3.174.1; Thu, 4 Dec 2014 13:54:23 -0800 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP1.corp.ad.broadcom.com (10.9.207.51) with Microsoft SMTP Server id 14.3.174.1; Thu, 4 Dec 2014 13:54:21 -0800 Received: from mail.broadcom.com (lbrmn-lnxub44.ric.broadcom.com [10.136.8.49]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 9D8C040FE5; Thu, 4 Dec 2014 13:53:47 -0800 (PST) From: Ray Jui To: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , Kumar Gala , "Linus Walleij" , Grant Likely , Christian Daudt , Matt Porter , Florian Fainelli , Russell King CC: Scott Branden , , , , , , "Ray Jui" Subject: [PATCH 1/4] pinctrl: Broadcom Cygnus pinctrl device tree binding Date: Thu, 4 Dec 2014 13:56:08 -0800 Message-ID: <1417730171-30455-2-git-send-email-rjui@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1417730171-30455-1-git-send-email-rjui@broadcom.com> References: <1417730171-30455-1-git-send-email-rjui@broadcom.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Device tree binding documentation for Broadcom Cygnus pinctrl driver Signed-off-by: Ray Jui Reviewed-by: Scott Branden --- .../bindings/pinctrl/brcm,cygnus-pinctrl.txt | 92 ++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinctrl.txt new file mode 100644 index 0000000..86e4579 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinctrl.txt @@ -0,0 +1,92 @@ +Broadcom Cygnus Pin Controller + +The Cygnus pin controller supports setting the alternate functions of groups +of pins. Pinmux configuration on individual pins is not supported by the +Cygnus A0 SoC. + +Required properties: + +- compatible: + Must be "brcm,cygnus-pinctrl" + +- reg: + Define the base and range of the I/O address space that contain the Cygnus +pin control registers + +- brcm,groups: + This can be strings of one or more group names. This defines the group(s) +that one wants to configure + +- brcm,function: + This is the alternate function that one wants to configure to. Valid +alternate functions are "alt1", "alt2", "alt3", "alt4" + +Each child node represents a configuration. Client devices reference the the +child node to enable the mux configuration. + +For example: + + pinctrl: pinctrl@0x0301d0c8 { + compatible = "brcm,cygnus-pinctrl"; + reg = <0x0301d0c8 0x2c>; + + i2s_0: i2s_0 { + brcm,groups = "smart_card0", "smart_card0_fcb"; + brcm,function = "alt2"; + }; + + i2s_1: i2s_1 { + brcm,groups = "smart_card1", "smart_card1_fcb"; + brcm,function = "alt2"; + }; + + spi_0: spi_0 { + brcm,groups = "spi0"; + brcm,function = "alt1"; + }; + } + + spi0@18028000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x18028000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + pinctrl-0 = <&spi_0>; + clocks = <&axi81_clk>; + clock-names = "apb_pclk"; + }; + +Consider the following snapshot of Cygnus pinmux table: + +number pin group alt1 alt2 alt3 alt4 +------ --- ---- ---- ---- ---- ---- +42 sc0_clk smart_card0 SMART CARD0 I2S_0 N/A chip_gpio24 +43 sc0_cmdvcc_l smart_card0 SMART CARD0 I2S_0 N/A STRAP +44 sc0_detect smart_card0 SMART CARD0 I2S_0 N/A chip_gpio25 +45 sc0_fcb smart_card0_fcb SMART CARD0_FCB I2S_0 N/A chip_gpio26 +46 sc0_io smart_card0 SMART CARD0 I2S_0 N/A chip_gpio27 +47 sc0_rst_l smart_card0 SMART CARD0 SPDIF N/A STRAP + +Note due to limitation of the Cygnus hardware, pinmux configuration can only +be group based. To enable I2S_0 function, one needs the following child node +configuration: + + i2s_0: i2s_0 { + brcm,groups = "smart_card0", "smart_card0_fcb"; + brcm,function = "alt2"; + }; + +This tells the Cygnus pin controller to configure groups "smart_card0" and +"smart_card0_fcb" to I2S_0. With this configuration, pins 42, 43, 44, 45, 46 +become I2C_0, and pin 47 becomes SPDIF + +Consider another example, that one wants to configure the above pins as GPIO: + + gpio_24_27: gpio_24_27 { + brcm,groups = "smart_card0", "smart_card0_fcb"; + brcm,function = "alt4"; + }; + +With the above configuration, pins 42, 44, 45, 46 become GPIO, and 43 and 47 +become reserved for STRAP