From patchwork Tue Nov 25 00:17:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 414186 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6526A140187 for ; Tue, 25 Nov 2014 11:19:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751572AbaKYARl (ORCPT ); Mon, 24 Nov 2014 19:17:41 -0500 Received: from mail-pd0-f201.google.com ([209.85.192.201]:50744 "EHLO mail-pd0-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751267AbaKYARh (ORCPT ); Mon, 24 Nov 2014 19:17:37 -0500 Received: by mail-pd0-f201.google.com with SMTP id ft15so1578253pdb.2 for ; Mon, 24 Nov 2014 16:17:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=81LEJQYPF3xfTFohH+bNaj3Gug+IZ8SiJqSXU+LmGps=; b=BpaYYqB0RXXRFg+3RwCkxSDUOj2zCwYbVPbcC1RYshlGHq+sPoeNNbWDCjPSjp0TL3 v7CMUBONvd91hJqGVca5FnNN2MMUyx1QlmZZX5fEzsG7C2CAtn9MjR8lfAGqDznF6SNm kz1kz52MNPFCwJL4srvVuIH7y4oRqirtGc/oUFn/+XuWHEMlyOamef64172b1Q3uXr9x WqiPgigVqU6IUsxfd9vtS22CCyNBjrTcARlB05tQLcfGuLi5+EHakSw4dg2zQJzz7bWR gAXK85XOFaEssUeiiaZjfEjn8T5lls4fGXa0PagNuLqQzSgzPCvotuD2v0azdUxPq5Gt oTUQ== X-Gm-Message-State: ALoCoQlSbUtElc9aU+ceVp7XRWesF9ZQmdnyue7NA9sUICH/2JE9ALUIc/nG8R8HyC+OyuHT+ILF X-Received: by 10.66.222.135 with SMTP id qm7mr22995319pac.20.1416874657250; Mon, 24 Nov 2014 16:17:37 -0800 (PST) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id 5si512449yhd.6.2014.11.24.16.17.35 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 24 Nov 2014 16:17:37 -0800 (PST) Received: from abrestic.mtv.corp.google.com ([172.22.65.70]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id 5pYwhUWo.1; Mon, 24 Nov 2014 16:17:37 -0800 Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 1D0B4220E40; Mon, 24 Nov 2014 16:17:35 -0800 (PST) From: Andrew Bresticker To: Stephen Warren , Thierry Reding , Alexandre Courbot , linux-tegra@vger.kernel.org Cc: Andrew Bresticker , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Jassi Brar , Linus Walleij , Greg Kroah-Hartman , Mathias Nyman , Grant Likely , Alan Stern , Arnd Bergmann , Olof Johansson , Kishon Vijay Abraham I , Felipe Balbi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org Subject: [PATCH V6 06/12] of: Update Tegra XUSB pad controller binding for USB Date: Mon, 24 Nov 2014 16:17:18 -0800 Message-Id: <1416874644-12070-7-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1416874644-12070-1-git-send-email-abrestic@chromium.org> References: <1416874644-12070-1-git-send-email-abrestic@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new bindings used for USB support by the Tegra XUSB pad controller. This includes additional PHY types, USB-specific pinconfig properties, etc. Signed-off-by: Andrew Bresticker Acked-by: Linus Walleij Reviewed-by: Stephen Warren --- No changes from v5. Changes from v4: - nvidia,usb2-port-num -> nvidia,usb2-port - Made usb3-port a pinconfig property - Adjusted property descriptions as suggested by Thierry. No changes from v3. Changes from v2: - Added nvidia,otg-hs-curr-level-offset property. - Dropped "-otg" from VBUS supplies. - Added mbox-names property. - Removed extra whitespace. Changes from v1: - Updated to use common mailbox bindings. - Made USB3 port-to-lane mappins a top-level binding rather than a pinconfig binding. - Add #defines for the padctl lanes. --- .../pinctrl/nvidia,tegra124-xusb-padctl.txt | 63 +++++++++++++++++++--- include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 +++ 2 files changed, 64 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt index 2f9c0bd..80895d1 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt @@ -21,6 +21,15 @@ Required properties: - padctl - #phy-cells: Should be 1. The specifier is the index of the PHY to reference. See for the list of valid values. +- mboxes: Must contain an entry for the XUSB mailbox channel. + See ../mailbox/mailbox.txt for details. +- mbox-names: Must include the following entries: + - xusb + +Optional properties: +------------------- +- vbus-{0,1,2}-supply: VBUS regulator for the corresponding UTMI pad. +- vddio-hsic-supply: VDDIO regulator for the HSIC pads. Lane muxing: ------------ @@ -50,26 +59,46 @@ Optional properties: pin or group should be assigned to. Valid values for function names are listed below. - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes) +- nvidia,usb2-port: USB2 port (0, 1, or 2) to which the lane is mapped. +- nvidia,usb3-port: USB3 port (0 or 1) to which the lane is mapped. +- nvidia,hsic-strobe-trim: HSIC strobe trimmer value. +- nvidia,hsic-rx-strobe-trim: HSIC RX strobe trimmer value. (0 - 7) +- nvidia,hsic-rx-data-trim: HSIC RX data trimmer value. (0 - 7) +- nvidia,hsic-tx-rtune-n: HSIC TX RTUNEN value. (0 - 7) +- nvidia,hsic-tx-rtune-p: HSIC TX RTUNEP value. (0 - 7) +- nvidia,hsic-tx-slew-n: HSIC TX SLEWN value. (0 - 7) +- nvidia,hsic-tx-slew-p: HSIC TX SLEWP value. (0 - 7) +- nvidia,hsic-auto-term: Enables HSIC AUTO_TERM. (0: no, 1: yes) +- nvidia,otg-hs-curr-level-offset: Offset to be applied to the pad's fused + HS_CURR_LEVEL value. (0 - 63) Note that not all of these properties are valid for all lanes. Lanes can be -divided into three groups: +divided into four groups: - otg-0, otg-1, otg-2: Valid functions for this group are: "snps", "xusb", "uart", "rsvd". - The nvidia,iddq property does not apply to this group. + Only the nvidia,otg-hs-curr-level-offset property applies. + + - ulpi-0: - - ulpi-0, hsic-0, hsic-1: + Valid functions for this group are: "snps", "xusb". + + - hsic-0, hsic-1: Valid functions for this group are: "snps", "xusb". - The nvidia,iddq property does not apply to this group. + Only the nvidia,hsic-* properties apply, and only when the function is + xusb. - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0: Valid functions for this group are: "pcie", "usb3", "sata", "rsvd". + Only the nvidia,iddq, nvidia,usb2-port, and nvidia,usb3-port properties + apply. The nvidia,usb2-port and nvidia,usb3-port properties are required + when the function is usb3. Example: ======== @@ -82,6 +111,8 @@ SoC file extract: reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; reset-names = "padctl"; + mboxes = <&xusb_mbox>; + mbox-names = "xusb"; #phy-cells = <1>; }; @@ -100,15 +131,35 @@ Board file extract: ... + usb@0,70090000 { + ... + + phys = <&padctl 5>, <&padctl 6>, <&padctl 7>; + phy-names = "utmi-1", "utmi-2", "usb3-0"; + + ... + } + + ... + padctl: padctl@0,7009f000 { pinctrl-0 = <&padctl_default>; pinctrl-names = "default"; + vbus-2-supply = <&vdd_usb3_vbus>; + padctl_default: pinmux { - usb3 { - nvidia,lanes = "pcie-0", "pcie-1"; + otg { + nvidia,lanes = "otg-1", "otg-2"; + nvidia,function = "xusb"; + }; + + usb3p0 { + nvidia,lanes = "pcie-0"; nvidia,function = "usb3"; nvidia,iddq = <0>; + nvidia,usb2-port = <2>; + nvidia,usb3-port = <0>; }; pcie { diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h index 914d56d..c83a4d4 100644 --- a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h +++ b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h @@ -3,5 +3,12 @@ #define TEGRA_XUSB_PADCTL_PCIE 0 #define TEGRA_XUSB_PADCTL_SATA 1 +#define TEGRA_XUSB_PADCTL_USB3_P0 2 +#define TEGRA_XUSB_PADCTL_USB3_P1 3 +#define TEGRA_XUSB_PADCTL_UTMI_P0 4 +#define TEGRA_XUSB_PADCTL_UTMI_P1 5 +#define TEGRA_XUSB_PADCTL_UTMI_P2 6 +#define TEGRA_XUSB_PADCTL_HSIC_P0 7 +#define TEGRA_XUSB_PADCTL_HSIC_P1 8 #endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */