From patchwork Thu Nov 13 12:56:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 410409 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D4DD31400DD for ; Thu, 13 Nov 2014 23:58:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933251AbaKMM5h (ORCPT ); Thu, 13 Nov 2014 07:57:37 -0500 Received: from regular1.263xmail.com ([211.150.99.133]:35844 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933195AbaKMM46 (ORCPT ); Thu, 13 Nov 2014 07:56:58 -0500 Received: from andy.yan?rock-chips.com (unknown [192.168.167.192]) by regular1.263xmail.com (Postfix) with SMTP id A74B66F02; Thu, 13 Nov 2014 20:56:53 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 9E6C81E80D; Thu, 13 Nov 2014 20:56:44 +0800 (CST) X-RL-SENDER: andy.yan@rock-chips.com X-FST-TO: airlied@linux.ie X-SENDER-IP: 127.0.0.1 X-LOGIN-NAME: andy.yan@rock-chips.com X-UNIQUE-TAG: <1c97ffa66988b810a0b8fcda4319af76> X-ATTACHMENT-NUM: 0 X-SENDER: yxj@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [127.0.0.1]) by smtp.263.net (Postfix) whith ESMTP id 8320A1JYP7; Thu, 13 Nov 2014 20:56:46 +0800 (CST) From: Andy Yan To: airlied@linux.ie, heiko@sntech.de, fabio.estevam@freescale.com, rmk+kernel@arm.linux.org.uk Cc: Greg Kroah-Hartman , Grant Likely , Rob Herring , Philipp Zabel , Shawn Guo , Andy yan , Josh Boyer , Sean Paul , Inki Dae , Dave Airlie , Arnd Bergmann , Lucas Stach , Zubair.Kakakhel@imgtec.com, djkurtz@google.com, ykk@rock-chips.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devel@driverdev.osuosl.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, jay.xu@rock-chips.com, Pawel Moll , mark.yao@rock-chips.com, Mark Rutland , Ian Campbell , Kumar Gala Subject: [PATCH v9 8/9] dt-bindings: Add documentation for rockchip dw hdmi Date: Thu, 13 Nov 2014 20:56:41 +0800 Message-Id: <1415883401-3708-1-git-send-email-andy.yan@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415793593-5075-1-git-send-email-andy.yan@rock-chips.com> References: <1415793593-5075-1-git-send-email-andy.yan@rock-chips.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Andy Yan --- Changes in v9: None Changes in v8: - Add documentation for rockchip dw hdmi Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None .../devicetree/bindings/video/dw_hdmi-rockchip.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/video/dw_hdmi-rockchip.txt diff --git a/Documentation/devicetree/bindings/video/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/video/dw_hdmi-rockchip.txt new file mode 100644 index 0000000..6ea6764 --- /dev/null +++ b/Documentation/devicetree/bindings/video/dw_hdmi-rockchip.txt @@ -0,0 +1,43 @@ +Rockchip specific extensions to the Synopsys Designware HDMI +================================ + +Required properties: +- compatible: "rockchip,rk3288-dw-hdmi"; +- reg: physical base address of the controller and length +- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing +- clocks: from common clock binding: handle to hdmi clock. +- clock-names: should be "clk" "hdcp_clk" +- rockchip,grf: this soc should set GRF regs to mux vopl/vopb. +- interrupts: HDMI interrupt number +- ports: contain a port node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. For + vopb,set the reg = <0> and set the reg = <1> for vopl. +- reg-io-width: the width of the reg:1,4, the value should be 4 on + rk3288 platform + +Example: +hdmi: hdmi@ff980000 { + compatible = "rockchip,rk3288-dw-hdmi"; + reg = <0xff980000 0x20000>; + reg-io-width = <4>; + ddc-i2c-bus = <&i2c5>; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; + clock-names = "clk", "hdcp_clk"; + status = "disabled"; + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; + }; + }; + }; +};