From patchwork Tue Oct 28 22:27:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 404360 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 7DC2D140085 for ; Wed, 29 Oct 2014 09:29:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755249AbaJ1W2G (ORCPT ); Tue, 28 Oct 2014 18:28:06 -0400 Received: from mail-pd0-f202.google.com ([209.85.192.202]:59966 "EHLO mail-pd0-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755248AbaJ1W2B (ORCPT ); Tue, 28 Oct 2014 18:28:01 -0400 Received: by mail-pd0-f202.google.com with SMTP id ft15so315078pdb.3 for ; Tue, 28 Oct 2014 15:28:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wvl3MerHoIttpcaURlzkuq1DOfLHgj6WQoXY5hdGOxE=; b=P/NdygqqB0eUISqN/bDZWf1aVqVSmOJqyzRpzDo6Ddv57d0/OAv3TDHWOiLB1iILDm j7YD/8w1MpJkRGuE56VVWfw0mhkmP4eniB9tSe0MVQ1ptobzBDwANaHkCoqd0XoDdPeA bS+j8ChJtlDdzYJaE78h6iMeEnsJQiks5/fAP+39nV/GMbSeq/uRSqgrpOVaj+4rsM1l AI0vbcRnq9Cu48L5ost1g3LjCYmxhzyYseikjneBxzEynIZfST0UoX1tJa1VOwg35AKF 3BLUNimWzfDmbQFz8iDvUcklzwyl4FqBhSmcc8nuElKZCY6qJKT8NLkFTPWPZCMx5JTA LAoA== X-Gm-Message-State: ALoCoQndJkqVug10WntlsYipYyzKCjSltJIpmqVGkXssDIlxXuNqqj1pezZ5MVgJWJtoHN38C7eG X-Received: by 10.68.192.102 with SMTP id hf6mr4167299pbc.3.1414535280750; Tue, 28 Oct 2014 15:28:00 -0700 (PDT) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id t28si177237yhb.4.2014.10.28.15.27.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Oct 2014 15:28:00 -0700 (PDT) Received: from abrestic.mtv.corp.google.com ([172.22.65.70]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id fP1AI9fA.1; Tue, 28 Oct 2014 15:28:00 -0700 Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id D3C34220E88; Tue, 28 Oct 2014 15:27:58 -0700 (PDT) From: Andrew Bresticker To: Stephen Warren , Thierry Reding , linux-tegra@vger.kernel.org Cc: Andrew Bresticker , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Jassi Brar , Linus Walleij , Greg Kroah-Hartman , Mathias Nyman , Grant Likely , Alan Stern , Arnd Bergmann , Kishon Vijay Abraham I , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org Subject: [PATCH RESEND V4 1/9] of: Add NVIDIA Tegra XUSB mailbox binding Date: Tue, 28 Oct 2014 15:27:48 -0700 Message-Id: <1414535277-15645-2-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1414535277-15645-1-git-send-email-abrestic@chromium.org> References: <1414535277-15645-1-git-send-email-abrestic@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device-tree bindings for the Tegra XUSB mailbox which will be used for communication between the Tegra xHCI controller's firmware and the host processor. Signed-off-by: Andrew Bresticker Reviewed-by: Stephen Warren --- No changes from v3. Changes from v2: - Dropped channel specifier. - Added pointer to mailbox documentation. Changes from v1: - Updated to use common mailbox bindings. --- .../bindings/mailbox/nvidia,tegra124-xusb-mbox.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt new file mode 100644 index 0000000..b35ea6e --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt @@ -0,0 +1,32 @@ +NVIDIA Tegra XUSB mailbox +========================= + +The Tegra XUSB mailbox is used by the Tegra xHCI controller's firmware to +communicate requests to the host and PHY drivers. + +Refer to ./mailbox.txt for generic information about mailbox device-tree +bindings. + +Required properties: +-------------------- + - compatible: Should be "nvidia,tegra124-xusb-mbox". + - reg: Address and length of the XUSB FPCI registers. + - interrupts: XUSB mailbox interrupt. + - #mbox-cells: Should be 0. There is only one physical channel. + +Example: +-------- + xusb_mbox: mailbox@0,70098000 { + compatible = "nvidia,tegra124-xusb-mbox"; + reg = <0x0 0x70098000 0x0 0x1000>; + interrupts = ; + + #mbox-cells = <0>; + }; + + usb@0,70090000 { + ... + mboxes = <&xusb_mbox>; + mbox-names = "xusb"; + ... + };