From patchwork Tue Oct 28 10:53:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sherlock Wang X-Patchwork-Id: 404171 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5FC12140077 for ; Tue, 28 Oct 2014 21:55:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753982AbaJ1Kyv (ORCPT ); Tue, 28 Oct 2014 06:54:51 -0400 Received: from mail-pd0-f179.google.com ([209.85.192.179]:52284 "EHLO mail-pd0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753897AbaJ1Kys (ORCPT ); Tue, 28 Oct 2014 06:54:48 -0400 Received: by mail-pd0-f179.google.com with SMTP id g10so419251pdj.38 for ; Tue, 28 Oct 2014 03:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mvaf9MK4vSbuytqan4pwgRmeTwKr8+LNhkE4vJJuoNs=; b=wOu0ZLkZZGEFmbGpVaeKSFvWoSBZ2z17Ycmf95blwd4+T3kSqjBAWcZjWjo+pM/W6f A1Yh+0lDwp6hQsUnXNa3YSjG8I7S9dX8MPGxBZh/OcrHBVvCOmfq0OyIw0Fnp0jDaAAm yIC2hNhplRmXQQTzaquXKk8Pt5N5gjop/irUd+rQRbPeuDevYUjJL52hEZla4kilO74p SJmY489SDKkC+JV0nH9jXkjlb6IpqwcjqCONT9uwd74a8NGf16DphOo560TwfRncpzZp f1plEmYmTL46SwIj282KZy94Uyyx32fc75/gJcUjrHou1rYnR6DNLZCGXWht0xvEKZrP mKnA== X-Received: by 10.70.100.138 with SMTP id ey10mr2785472pdb.38.1414493687476; Tue, 28 Oct 2014 03:54:47 -0700 (PDT) Received: from localhost.localdomain ([58.251.159.252]) by mx.google.com with ESMTPSA id l5sm1368832pdj.12.2014.10.28.03.54.39 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 03:54:46 -0700 (PDT) From: Zhou Wang To: David Woodhouse , Brian Norris , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org Cc: mark.rutland@arm.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, robh+dt@kernel.org, galak@codeaurora.org, caizhiyong@huawei.com, haojian.zhuang@gmail.com, xuwei5@hisilicon.com, wangzhou1@hisilicon.com, linux-kernel@vger.kernel.org, Zhou Wang Subject: [PATCH v3 2/2] mtd: hisilicon: add device tree binding documentation Date: Tue, 28 Oct 2014 18:53:49 +0800 Message-Id: <1414493629-12570-3-git-send-email-wangzhou.bry@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1414493629-12570-1-git-send-email-wangzhou.bry@gmail.com> References: <1414493629-12570-1-git-send-email-wangzhou.bry@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Zhou Wang --- .../devicetree/bindings/mtd/hisi504-nand.txt | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/hisi504-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/hisi504-nand.txt b/Documentation/devicetree/bindings/mtd/hisi504-nand.txt new file mode 100644 index 0000000..c8b3988 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/hisi504-nand.txt @@ -0,0 +1,40 @@ +Hisilicon Hip04 Soc NAND controller DT binding + +Required properties: +- compatible: Should be "hisilicon,504-nfc". +- reg: The first contains base physical address and size of + NAND controller's registers. The second contains base + physical address and size of NAND controller's buffer. +- interrupts: Interrupt number for nfc. +- nand-bus-width: See nand.txt. +- nand-ecc-mode: See nand.txt. +- hisi,nand-ecc-bits: ECC bits type support. + <0>: none ecc + <1>: Can correct 1bit per 512byte. + <6>: Can correct 16bits per 1K byte. +- #address-cells: partition address, should be set 1. +- #size-cells: partition size, should be set 1. + +Flash chip may optionally contain additional sub-nodes describing partitions of +the address space. See partition.txt for more detail. + +Example: + + nand: nand@4020000 { + compatible = "hisilicon,504-nfc"; + reg = <0x4020000 0x10000>, <0x5000000 0x1000>; + interrupts = <0 379 4>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + hisi,nand-ecc-bits = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "nand_text"; + reg = <0x00000000 0x00400000>; + }; + + ... + + };