From patchwork Tue Oct 21 14:45:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 401554 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ED8614001A for ; Wed, 22 Oct 2014 01:49:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755426AbaJUOrm (ORCPT ); Tue, 21 Oct 2014 10:47:42 -0400 Received: from mail-wi0-f175.google.com ([209.85.212.175]:61315 "EHLO mail-wi0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755406AbaJUOrk (ORCPT ); Tue, 21 Oct 2014 10:47:40 -0400 Received: by mail-wi0-f175.google.com with SMTP id d1so10346218wiv.14 for ; Tue, 21 Oct 2014 07:47:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ywR1GJ3Prn3vvKiDSC1q9uT2CLo0RABXtbBUs1oZCzg=; b=JsFvNFoGR/Sc9pkmeu+nIAiFPBfQc7L4KtQkmhbWJ0J3STJmdxilNNOYYM2KnF2Mmt IRZeOfZago97IuvgUmaGv6PUysy0EC01p1p9tOBNhQ2xNQoi4ugSuzwqSLx5Y2cImtYd EvyIISjsOugIonDMdmhahp6H4k5uQyWdSsrwJTKM7bYz7muqNK7URrP6muwSAjWPObye L4B5zT1Ean2u64ud+gADZgYF3/0Te3KvZUl4rCpxAEWUlYjrhDL/+Uj+l+TgEnL7iPHF 5XE5/ZWoJU8QTLAdJRm0eqIPdbIpHxpyzvZPjdxzvH9wUpm0acvON4UIXW08hJ3FFlJK LMnA== X-Received: by 10.194.221.105 with SMTP id qd9mr43525196wjc.51.1413902858609; Tue, 21 Oct 2014 07:47:38 -0700 (PDT) Received: from cizrna.lan (37-48-37-232.tmcz.cz. [37.48.37.232]) by mx.google.com with ESMTPSA id b6sm13322927wiy.22.2014.10.21.07.47.35 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Oct 2014 07:47:37 -0700 (PDT) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Javier Martinez Canillas , Tomeu Vizoso , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Alexandre Courbot , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/12] of: Document timings subnode of nvidia,tegra-mc Date: Tue, 21 Oct 2014 16:45:37 +0200 Message-Id: <1413902788-7727-6-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1413902788-7727-1-git-send-email-tomeu.vizoso@collabora.com> References: <1413902788-7727-1-git-send-email-tomeu.vizoso@collabora.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The MC driver needs some timing-specific information to program the EMEM during a rate change of the EMC clock. Signed-off-by: Tomeu Vizoso --- .../memory-controllers/nvidia,tegra-mc.txt | 46 +++++++++++++++++++++- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt index f3db93c..8467b8c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt @@ -15,9 +15,26 @@ Required properties: This device implements an IOMMU that complies with the generic IOMMU binding. See ../iommu/iommu.txt for details. -Example: --------- +The node should contain a "timings" subnode for each supported RAM type (see +field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address being its +RAM_CODE. +Required properties for "timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used +for. + +Each "timings" node should contain a "timing" subnode for every supported EMC +clock rate. The "timing" subnodes should have the clock rate in Hz as their unit +address. + +Required properties for "timing" nodes : +- clock-frequency : Should contain the memory clock rate in Hz. +- nvidia,emem-configuration : Values to be written to the EMEM register block, +as specified by the board documentation. + +Example SoC include file: + +/ { mc: memory-controller@0,70019000 { compatible = "nvidia,tegra124-mc"; reg = <0x0 0x70019000 0x0 0x1000>; @@ -34,3 +51,28 @@ Example: ... iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; }; +}; + +Example board file: + +/ { + memory-controller@0,70019000 { + timings@3 { + nvidia,ram-code = <3>; + + timing@12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + >; + }; + }; + }; +};