From patchwork Tue Oct 21 14:45:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 401559 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 1B4FB14001A for ; Wed, 22 Oct 2014 01:50:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933120AbaJUOrZ (ORCPT ); Tue, 21 Oct 2014 10:47:25 -0400 Received: from mail-wg0-f49.google.com ([74.125.82.49]:34754 "EHLO mail-wg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932353AbaJUOrX (ORCPT ); Tue, 21 Oct 2014 10:47:23 -0400 Received: by mail-wg0-f49.google.com with SMTP id x12so1525891wgg.8 for ; Tue, 21 Oct 2014 07:47:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=EEb1TRd7cIyCFlmDAvsz7EIJIo6kyAlDZ8lFvBVmTEU=; b=a/SEkuEnN9QZK70RnLgPdLMgwg+iKnF7ZAw3dhTCdYYuyn2gk3pySf3cIDiCe9Uek5 4wGSo5O7s8ylXg7TvX1rRaJ02ozc8Ye1pBEwzWKZP89py+Ljw0zv0ST0R0VG1bIPnbq0 DUgRPmpUnQKfq8uyk0cxyUE8Mj+VFQSNfNWhDvjl40Ef33tQ3vWhWOL7SuCqnmXeLaeN ldP+Hj50oNn91UsovnBeeUc3hh5hOR8BwhcCdfXaK7vWmxOSOT3a49qF0lBnwClAKUWh HdHSlj8Sd8BZcj+PJtOsExb82z8vrKLgNHz4UGzCza9rPuRs00ZgUgUXPyEIl9MQsCkL yOAg== X-Received: by 10.180.36.48 with SMTP id n16mr30283252wij.6.1413902840193; Tue, 21 Oct 2014 07:47:20 -0700 (PDT) Received: from cizrna.lan (37-48-37-232.tmcz.cz. [37.48.37.232]) by mx.google.com with ESMTPSA id b6sm13322927wiy.22.2014.10.21.07.47.17 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Oct 2014 07:47:19 -0700 (PDT) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Javier Martinez Canillas , Tomeu Vizoso , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Alexandre Courbot , Peter De Schrijver , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/12] of: Document long-ram-code property in nvidia, tegra20-apbmisc Date: Tue, 21 Oct 2014 16:45:34 +0200 Message-Id: <1413902788-7727-3-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1413902788-7727-1-git-send-email-tomeu.vizoso@collabora.com> References: <1413902788-7727-1-git-send-email-tomeu.vizoso@collabora.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Needed to properly decode the ram code register. Signed-off-by: Tomeu Vizoso --- Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index b97b8be..e2562ed 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -11,3 +11,6 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: boolean that tells whether the ram code is long (4 bit) + or short (2 bit). If not present, false.