| Message ID | 1412945262-6068-3-git-send-email-tomeu.vizoso@collabora.com |
|---|---|
| State | Needs Review / ACK, archived |
| Headers | show |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 1 errors, 0 warnings, 0 lines checked |
| robh/patch-applied | success |
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index b97b8be..e2562ed 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -11,3 +11,6 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: boolean that tells whether the ram code is long (4 bit) + or short (2 bit). If not present, false.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 3 +++ 1 file changed, 3 insertions(+)