From patchwork Fri May 23 07:51:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 351771 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2BEAE140086 for ; Fri, 23 May 2014 18:34:12 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752069AbaEWIds (ORCPT ); Fri, 23 May 2014 04:33:48 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:39569 "EHLO mirror2.csie.ntu.edu.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751696AbaEWI1k (ORCPT ); Fri, 23 May 2014 04:27:40 -0400 Received: from wens by mirror2.csie.ntu.edu.tw with local (Exim 4.82) (envelope-from ) id 1WnkGU-0007SU-Kz; Fri, 23 May 2014 15:51:42 +0800 From: Chen-Yu Tsai To: Greg Kroah-Hartman , Samuel Ortiz , Lee Jones , Maxime Ripard , Rob Herring , Mike Turquette , Emilio Lopez , Linus Walleij Cc: Chen-Yu Tsai , linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans de Goede , Boris BREZILLON , Luc Verhaegen Subject: [PATCH 10/22] clk: sunxi: Add support for PLL6 pre-divider on AHB1 clock Date: Fri, 23 May 2014 15:51:13 +0800 Message-Id: <1400831485-28576-11-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.0.0.rc2 In-Reply-To: <1400831485-28576-1-git-send-email-wens@csie.org> References: <1400831485-28576-1-git-send-email-wens@csie.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On the A31 and A23, the PLL6 input to the AHB1 clock has a 2 bit wide pre-divider. This was verified from the A23 user manual and A31/A23 SDK sources. Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/clock/sunxi.txt | 2 ++ drivers/clk/sunxi/clk-sunxi.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index b9ec668..ae18ec1 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -21,6 +21,8 @@ Required properties: "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 + "allwinner,sun6i-a31-ahb1-pll6-clk" - for the PLL6 pre-divider to + AHB1 on A31 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 339cabc..89eadbc 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -686,6 +686,12 @@ static const struct div_data sun4i_apb0_data __initconst = { .width = 2, }; +static const struct div_data sun6i_a31_ahb1_pll6_data __initconst = { + .shift = 6, + .pow = 0, + .width = 2, +}; + static const struct div_data sun6i_a31_apb2_div_data __initconst = { .shift = 0, .pow = 0, @@ -1128,6 +1134,7 @@ static const struct of_device_id clk_div_match[] __initconst = { {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,}, {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,}, {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,}, + {.compatible = "allwinner,sun6i-a31-ahb1-pll6-clk", .data = &sun6i_a31_ahb1_pll6_data,}, {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,}, {} };