From patchwork Tue May 20 17:40:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 350803 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 28321140088 for ; Wed, 21 May 2014 03:41:48 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754124AbaETRld (ORCPT ); Tue, 20 May 2014 13:41:33 -0400 Received: from mail-ie0-f176.google.com ([209.85.223.176]:35967 "EHLO mail-ie0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754125AbaETRkO (ORCPT ); Tue, 20 May 2014 13:40:14 -0400 Received: by mail-ie0-f176.google.com with SMTP id rl12so787013iec.7 for ; Tue, 20 May 2014 10:40:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nNrcWUxU0HsL95yM4Dp1lksCS7xHSBXnyxN+QxCAP8g=; b=FZV6dUCb0nhcR74hYrhaOGWadfb3ei+oq2W58tJQDEv3sww6OvvtucDzIXai5cAfmX 0rUUmYuRkDEKxHyI854RLrJKypdL9rlBp+b+H0D3bwQt1T/NWUHH+oKiQk1TzSZigF4V qgcbgNeCQ9jBXMKXKNYiduNoKg50nmKi5WXrBlUCjKOL5VYLkNgEhOkr5OErTJn8JquS WWX7lXj4koJ06sU1g687bfTL/KeciKxLp/pXX7M8xWEt38AuWTiQpwo23mMENU1QH717 r2sp8SFFKj+Kg+j0vq/fygfzpU9sQoGZcc5Uho1KM1E4KrBL2AL++Se8yF9Be6QMazRZ JQSQ== X-Gm-Message-State: ALoCoQmd4JKBCg4mlfF9+zhl2o5+ywEYtKNeEOLfZAQ5KPBUtcgIifik1lS6WcsleusIA/qRmhBM X-Received: by 10.50.45.3 with SMTP id i3mr7106569igm.7.1400607613700; Tue, 20 May 2014 10:40:13 -0700 (PDT) Received: from localhost.localdomain (c-71-195-31-37.hsd1.mn.comcast.net. [71.195.31.37]) by mx.google.com with ESMTPSA id h7sm30470555igy.2.2014.05.20.10.40.12 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 20 May 2014 10:40:13 -0700 (PDT) From: Alex Elder To: mporter@linaro.org, bcm@fixthebug.org, linux@arm.linux.org.uk, devicetree@vger.kernel.org, arnd@arndb.de, sboyd@codeaurora.org Cc: bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, jason@lakedaemon.net, lorenzo.pieralisi@arm.com, mark.rutland@arm.com, pawel.moll@arm.com, rdunlap@infradead.org, rjui@broadcom.com, robh+dt@kernel.org, rvaswani@codeaurora.org Subject: [PATCH v4 1/5] devicetree: bindings: document Broadcom CPU enable method Date: Tue, 20 May 2014 12:40:02 -0500 Message-Id: <1400607606-10810-2-git-send-email-elder@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400607606-10810-1-git-send-email-elder@linaro.org> References: <1400607606-10810-1-git-send-email-elder@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Broadcom mobile SoCs use a ROM-implemented holding pen for controlled boot of secondary cores. A special register is used to communicate to the ROM that a secondary core should start executing kernel code. This enable method is currently used for members of the bcm281xx and bcm21664 SoC families. The use of an enable method also allows the SMP operation vector to be assigned as a result of device tree content for these SoCs. Signed-off-by: Alex Elder --- Documentation/devicetree/bindings/arm/cpus.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 333f4ae..c6a2411 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -185,6 +185,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "brcm,bcm11351-cpu-method" - cpu-release-addr Usage: required for systems that have an "enable-method" @@ -209,6 +210,17 @@ nodes to be present and contain the properties described below. Value type: Definition: Specifies the ACC[2] node associated with this CPU. + - secondary-boot-reg + Usage: + Required for systems that have an "enable-method" + property value of "brcm,bcm11351-cpu-method". + Value type: + Definition: + Specifies the physical address of the register used to + request the ROM holding pen code release a secondary + CPU. The value written to the register is formed by + encoding the target CPU id into the low bits of the + physical start address it should jump to. Example 1 (dual-cluster big.LITTLE system 32-bit):