From patchwork Thu May 8 03:12:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tang yuantian X-Patchwork-Id: 346879 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 1D89B1401AE for ; Thu, 8 May 2014 13:29:06 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752984AbaEHD3F (ORCPT ); Wed, 7 May 2014 23:29:05 -0400 Received: from mail-bn1blp0181.outbound.protection.outlook.com ([207.46.163.181]:45269 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752954AbaEHD3E (ORCPT ); Wed, 7 May 2014 23:29:04 -0400 Received: from BY2PR03CA028.namprd03.prod.outlook.com (10.242.234.149) by BY2PR03MB395.namprd03.prod.outlook.com (10.141.141.14) with Microsoft SMTP Server (TLS) id 15.0.939.12; Thu, 8 May 2014 03:14:48 +0000 Received: from BN1AFFO11FD051.protection.gbl (2a01:111:f400:7c10::198) by BY2PR03CA028.outlook.office365.com (2a01:111:e400:2c2c::21) with Microsoft SMTP Server (TLS) id 15.0.939.12 via Frontend Transport; Thu, 8 May 2014 03:14:48 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD051.mail.protection.outlook.com (10.58.53.66) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Thu, 8 May 2014 03:14:48 +0000 Received: from titan.ap.freescale.net (udp143770uds.ap.freescale.net [10.192.208.233] (may be forged)) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s483Ed3Z021045; Wed, 7 May 2014 20:14:40 -0700 From: To: CC: , , "Tang Yuantian" Subject: [PATCH v2] clk: qoriq: Update the clock bindings Date: Thu, 8 May 2014 11:12:10 +0800 Message-ID: <1399518730-40458-1-git-send-email-Yuantian.Tang@freescale.com> X-Mailer: git-send-email 1.8.5 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(189002)(199002)(68736004)(69596002)(50986999)(84676001)(50226001)(44976005)(4396001)(88136002)(89996001)(31966008)(74662001)(87286001)(77982001)(48376002)(50466002)(87936001)(2009001)(99396002)(76482001)(97736001)(74502001)(46102001)(19580405001)(19580395003)(6806004)(83322001)(79102001)(92566001)(81156002)(81342001)(62966002)(85852003)(21056001)(93916002)(80022001)(86152002)(77096999)(47776003)(20776003)(64706001)(86362001)(83072002)(92726001)(36756003)(77156001)(81542001)(42866002); DIR:OUT; SFP:1101; SCL:1; SRVR:BY2PR03MB395; H:az84smr01.freescale.net; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 0205EDCD76 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Yuantian.Tang@freescale.com; X-OriginatorOrg: freescale.com Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tang Yuantian Main changs include: - Clarified the clock nodes' version number - Fixed a issue in example Singed-off-by: Tang Yuantian --- v2: - rename this binding - rewrite the description .../bindings/clock/{corenet-clock.txt => qoriq-clock.txt} | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) rename Documentation/devicetree/bindings/clock/{corenet-clock.txt => qoriq-clock.txt} (95%) diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt similarity index 95% rename from Documentation/devicetree/bindings/clock/corenet-clock.txt rename to Documentation/devicetree/bindings/clock/qoriq-clock.txt index 24711af..5666812 100644 --- a/Documentation/devicetree/bindings/clock/corenet-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -7,6 +7,14 @@ which can then be passed to a variety of internal logic, including cores and peripheral IP blocks. Please refer to the Reference Manual for details. +All references to "1.0" and "2.0" refer to the QorIQ chassis version to +which the chip complies. + +Chassis Version Example Chips +--------------- ------------- +1.0 p4080, p5020, p5040 +2.0 t4240, b4860, t1040 + 1. Clock Block Binding Required properties: @@ -85,7 +93,7 @@ Example for clock block and clock provider: #clock-cells = <0>; compatible = "fsl,qoriq-sysclk-1.0"; clock-output-names = "sysclk"; - } + }; pll0: pll0@800 { #clock-cells = <1>;