From patchwork Sat Apr 19 01:12:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 340442 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A862F1400F7 for ; Sat, 19 Apr 2014 11:13:24 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754781AbaDSBNV (ORCPT ); Fri, 18 Apr 2014 21:13:21 -0400 Received: from mail-pb0-f51.google.com ([209.85.160.51]:53398 "EHLO mail-pb0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754718AbaDSBNR (ORCPT ); Fri, 18 Apr 2014 21:13:17 -0400 Received: by mail-pb0-f51.google.com with SMTP id uo5so1922613pbc.24 for ; Fri, 18 Apr 2014 18:13:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=S/o6havm6G7Tt1edfXTycRqhKNw7hf0DoiOT943g3I4=; b=hDruKjvOwfunH7RGGGTWesWebNP6mqnR9yRCnMggpkonRg5ziMcVWIlVpN2X3VCDPu QSPCeY2e+dmrOXWlqjhiZryCv0p1C5DdisR1GNHGTm+KQ7zuEHJY/BHcVxJPTyT0ddxd ulO3F62LT0d81TSDFk1TNQAW1RZX1pFBPBEor5p2Av5nLef8vd+e0T6+bakl2j/OWyFG vVG99rEJksfxtTptlzIDtLj+hjwGjlMNY3ugW+hN/16EE4wmV168AiWlumb2K4sPDcBH 8pMYni4UZz/5LwdIKd8a9hBiDRtzKidt43cpO16bc9rifemd51T5vol7SlG645WmzXTo Q/0g== X-Gm-Message-State: ALoCoQlhygVK+1vZj+I7E62zf5sFbUZwMnAHc9r1HOND7CbWlM160z6dqgODhpQ2aSFVXfVmlIAK X-Received: by 10.66.230.193 with SMTP id ta1mr24913579pac.29.1397869996128; Fri, 18 Apr 2014 18:13:16 -0700 (PDT) Received: from localhost.localdomain ([120.136.42.84]) by mx.google.com with ESMTPSA id it4sm62508680pbc.39.2014.04.18.18.13.10 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 18 Apr 2014 18:13:15 -0700 (PDT) From: Zhangfei Gao To: davem@davemloft.net, linux@arm.linux.org.uk, arnd@arndb.de, f.fainelli@gmail.com, sergei.shtylyov@cogentembedded.com, mark.rutland@arm.com, David.Laight@ACULAB.COM, eric.dumazet@gmail.com, xuwei5@hisilicon.com Cc: linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, Zhangfei Gao Subject: [PATCH v8 1/3] Documentation: add Device tree bindings for Hisilicon hip04 ethernet Date: Sat, 19 Apr 2014 09:12:58 +0800 Message-Id: <1397869980-21187-2-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1397869980-21187-1-git-send-email-zhangfei.gao@linaro.org> References: <1397869980-21187-1-git-send-email-zhangfei.gao@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the Device Tree bindings for the Hisilicon hip04 Ethernet controller, including 100M / 1000M controller. Signed-off-by: Zhangfei Gao --- .../bindings/net/hisilicon-hip04-net.txt | 88 ++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt diff --git a/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt b/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt new file mode 100644 index 0000000..988fc69 --- /dev/null +++ b/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt @@ -0,0 +1,88 @@ +Hisilicon hip04 Ethernet Controller + +* Ethernet controller node + +Required properties: +- compatible: should be "hisilicon,hip04-mac". +- reg: address and length of the register set for the device. +- interrupts: interrupt for the device. +- port-handle: + phandle, specifies a reference to the syscon ppe node + port, port number connected to the controller + channel, recv channel start from channel * number (RX_DESC_NUM) +- phy-mode: see ethernet.txt [1]. + +Optional properties: +- phy-handle: see ethernet.txt [1]. + +[1] Documentation/devicetree/bindings/net/ethernet.txt + + +* Ethernet ppe node: +Control rx & tx fifos of all ethernet controllers. +Have 2048 recv channels shared by all ethernet controllers, only if no overlap. +Each controller's recv channel start from channel * number (RX_DESC_NUM). + +Required properties: +- compatible: "hisilicon,hip04-ppe", "syscon". +- reg: address and length of the register set for the device. + + +* MDIO bus node: + +Required properties: + +- compatible: should be "hisilicon,hip04-mdio". +- Inherits from MDIO bus node binding [2] +[2] Documentation/devicetree/bindings/net/phy.txt + +Example: + mdio { + compatible = "hisilicon,hip04-mdio"; + reg = <0x28f1000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + marvell,reg-init = <18 0x14 0 0x8001>; + }; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + marvell,reg-init = <18 0x14 0 0x8001>; + }; + }; + + ppe: ppe@28c0000 { + compatible = "hisilicon,hip04-ppe", "syscon"; + reg = <0x28c0000 0x10000>; + }; + + fe: ethernet@28b0000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x28b0000 0x10000>; + interrupts = <0 413 4>; + phy-mode = "mii"; + port-handle = <&ppe 31 0>; + }; + + ge0: ethernet@2800000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x2800000 0x10000>; + interrupts = <0 402 4>; + phy-mode = "sgmii"; + port-handle = <&ppe 0 1>; + phy-handle = <&phy0>; + }; + + ge8: ethernet@2880000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x2880000 0x10000>; + interrupts = <0 410 4>; + phy-mode = "sgmii"; + port-handle = <&ppe 8 2>; + phy-handle = <&phy1>; + };