From patchwork Sat Feb 15 02:22:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ravi Patel X-Patchwork-Id: 320598 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2FD5A2C00A4 for ; Sat, 15 Feb 2014 13:23:03 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752097AbaBOCWW (ORCPT ); Fri, 14 Feb 2014 21:22:22 -0500 Received: from exprod5og116.obsmtp.com ([64.18.0.147]:42162 "HELO exprod5og116.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1751738AbaBOCWU (ORCPT ); Fri, 14 Feb 2014 21:22:20 -0500 Received: from mail-pd0-f171.google.com ([209.85.192.171]) (using TLSv1) by exprod5ob116.postini.com ([64.18.4.12]) with SMTP ID DSNKUv7PW5yZfse6GebxcgatF5B/XmbPKxxR@postini.com; Fri, 14 Feb 2014 18:22:19 PST Received: by mail-pd0-f171.google.com with SMTP id g10so12690848pdj.2 for ; Fri, 14 Feb 2014 18:22:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mUwfOFLzTaNMh/efv9f8tXQKfiG7ZmeNRpRdEzvayWM=; b=HdOWTq6zxciFyRbrXYI3sRrp0e6LPtKIChMeCixeAvbb/uIJfvmI5YzVCw0QmXxelU K1ywBUhZyOow8iQXXsTHegOfOVUE6uuM8ig2OHtCfYu4spdi5QXuNcS38oN4flJyNukX U5cYhoZbdNDQIN4X6zwdEujTGHuMTGkuTi1Em3aEAX/iIea6GtBvcgDUoAACs403KVt9 R0hn9ZJ/b8VPz3DqSOuvDXIKvOsPs+hYE6NFzJZg98WYXnvwAGrn5xlP8+Y8RftD3eLK AiUERv8USO/eHpGKTl+V5aNNbM1IsGUngz4dZrA7y2pZhbtq6aOEZUi4yZ01opE0Stb4 P4iw== X-Gm-Message-State: ALoCoQnl7Qmd6qfaUQmmPRJP9NjarY9he4yRnL8HBLm0j3vJdos2MoOSO1OdugxUUF9M194h5lBaCVpa6XneLQePG9CvZ3uxmtTzPEIt3Oj4DawZNZhcegjRtZztErYl+LgZxWpCsHZLpq1dQFqWxqyQsQouOtfPCN8SlvzSXCDvxJK+DlgYVjU= X-Received: by 10.68.194.97 with SMTP id hv1mr12791893pbc.162.1392430939173; Fri, 14 Feb 2014 18:22:19 -0800 (PST) X-Received: by 10.68.194.97 with SMTP id hv1mr12791876pbc.162.1392430939053; Fri, 14 Feb 2014 18:22:19 -0800 (PST) Received: from amcclab-Precision-WorkStation-T3400.amcc.com (63-147-59-2.dia.static.qwest.net. [63.147.59.2]) by mx.google.com with ESMTPSA id rb6sm21926882pbb.41.2014.02.14.18.22.16 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 14 Feb 2014 18:22:17 -0800 (PST) From: Ravi Patel To: arnd@arndb.de, gregkh@linuxfoundation.org, davem@davemloft.net Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jcm@redhat.com, patches@apm.com, Ravi Patel , Keyur Chudgar Subject: [PATCH V3 2/4] Documentation: devicetree: bindings for APM X-Gene SoC QMTM Date: Fri, 14 Feb 2014 18:22:00 -0800 Message-Id: <1392430922-24643-3-git-send-email-rapatel@apm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1392430922-24643-1-git-send-email-rapatel@apm.com> References: <1392430922-24643-1-git-send-email-rapatel@apm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds devicetree bindings documentation for APM X-Gene SoC Queue Manager/Traffic Manager. Signed-off-by: Ravi Patel Signed-off-by: Keyur Chudgar --- .../devicetree/bindings/mailbox/apm-xgene-qmtm.txt | 53 ++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/apm-xgene-qmtm.txt diff --git a/Documentation/devicetree/bindings/mailbox/apm-xgene-qmtm.txt b/Documentation/devicetree/bindings/mailbox/apm-xgene-qmtm.txt new file mode 100644 index 0000000..cb17d5f --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/apm-xgene-qmtm.txt @@ -0,0 +1,53 @@ +* APM X-Gene SoC Queue Manager/Traffic Manager mailbox nodes + +Mailbox nodes are defined to describe on-chip Queue Managers in APM X-Gene SoC. +APM X-Gene SoC Ethernet, PktDMA (XOR Engine), and Security Engine subsystems +communicate with a central Queue Manager using messages which include +information about the work to be performed and the location of the associated +data buffers. There are multiple instances of QMTM. Each QMTM instance has its +own node. Its corresponding clock nodes are shown below. + +Required properties: +- compatible : Shall be "apm,xgene-qmtm" +- reg : First memory resource shall be the QMTM register + memory resource. + Second memory resource shall be the QMTM IO-Fabric + memory resource. +- #mailbox-cells : Shall be 4 as it expects following arguments + First cell for 64-bit mailbox bus address MSB. + Second cell for 64-bit mailbox bus address LSB. + Third cell for 32-bit mailbox size. + Fourth cell for 32-bit mailbox signal/id value. +- interrupts : First interrupt resource shall be the QMTM Error + interrupt. + Remaining interrupt resources shall be the Ingress + work message interrupt mapping for receiver, + receiving work messages for the QMTM. +- clocks : Reference to the clock entry. + +Optional properties: +- status : Shall be "ok" if enabled or "disabled" if disabled. + Default is "ok". + +Example: + qmlclk: qmlclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clock-names = "socplldiv2"; + status = "ok"; + csr-offset = <0x0>; + csr-mask = <0x3>; + enable-offset = <0x8>; + enable-mask = <0x3>; + }; + + qmlite: mailbox@17030000 { + compatible = "apm,xgene-qmtm"; + #mailbox-cells = <4>; + status = "ok"; + reg = <0x0 0x17030000 0x0 0x10000>, + <0x0 0x10000000 0x0 0x400000>; + interrupts = <0x0 0x40 0x4>, + <0x0 0x3c 0x4>; + clocks = <&qmlclk 0>; + };