From patchwork Wed Jan 29 14:34:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris Brezillon X-Patchwork-Id: 315052 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 01DB82C00B9 for ; Thu, 30 Jan 2014 01:35:32 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752754AbaA2Oev (ORCPT ); Wed, 29 Jan 2014 09:34:51 -0500 Received: from mail-ea0-f177.google.com ([209.85.215.177]:60005 "EHLO mail-ea0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752742AbaA2Oet (ORCPT ); Wed, 29 Jan 2014 09:34:49 -0500 Received: by mail-ea0-f177.google.com with SMTP id n15so976043ead.36 for ; Wed, 29 Jan 2014 06:34:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gTUmoZyZBdPMwlG6+0LjKPdwc4424LAXZccTKAoCMkY=; b=lmNTpJgFw0aQNNJJGZNkLyRbh3/r5JxcMPqADiEa1V+jzmvfqnUIXVeDroEelBT1Dp FVtLzLB/rU7l06PXknWtwxerMd83YCjngyFOLe94IrnfOG8QzYcaZ+9dUj3d3+D4vme7 LbqrSab0S5HauEIEHYQNixMGILS/EESnYpTBKY9wT1hAlYKC5betbHFaAGiqQW6khWNM Nr/BcAZNtLTzeciN+sLJbUCv+p6BU6qWWw0rWm9zgQ606KzK1xLzUPdBTYrMPky+QH0D 0jF34lREJ7N3hIPHfW+vyXOfxtvekIKYX7uI6JV0xnYztt4ld93J7SjKeSEl/nP44skf KDwg== X-Received: by 10.15.55.193 with SMTP id v41mr3049301eew.80.1391006088064; Wed, 29 Jan 2014 06:34:48 -0800 (PST) Received: from bbrezillon-laptop.int.overkiz.com ([80.245.18.66]) by mx.google.com with ESMTPSA id o43sm9435426eef.12.2014.01.29.06.34.45 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 29 Jan 2014 06:34:47 -0800 (PST) From: Boris BREZILLON To: Maxime Ripard , Rob Landley , Russell King , David Woodhouse , Grant Likely , Brian Norris , Jason Gunthorpe , Arnd Bergmann Cc: Boris BREZILLON , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mtd@lists.infradead.org, dev@linux-sunxi.org Subject: [RFC PATCH v2 09/14] mtd: nand: add sunxi NFC dt bindings doc Date: Wed, 29 Jan 2014 15:34:19 +0100 Message-Id: <1391006064-28890-10-git-send-email-b.brezillon.dev@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1391006064-28890-1-git-send-email-b.brezillon.dev@gmail.com> References: <1391006064-28890-1-git-send-email-b.brezillon.dev@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the sunxi NAND Flash Controller dt bindings documentation. Signed-off-by: Boris BREZILLON --- .../devicetree/bindings/mtd/sunxi-nand.txt | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/sunxi-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt new file mode 100644 index 0000000..b0e55a3 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt @@ -0,0 +1,46 @@ +Allwinner NAND Flash Controller (NFC) + +Required properties: +- compatible : "allwinner,sun4i-nand". +- reg : shall contain registers location and length for data and reg. +- interrupts : shall define the nand controller interrupt. +- #address-cells: shall be set to 1. Encode the nand CS. +- #size-cells : shall be set to 0. +- clocks : shall reference nand controller clocks. +- clock-names : nand controller internal clock names. Shall contain : + * "ahb_clk" : AHB gating clock + * "sclk" : nand controller clock + +Optional children nodes: +Children nodes represent the available nand chips. + +Optional properties: +- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI + standard. +- allwinner,rb : shall contain the native Ready/Busy ids. + or +- rb-gpios : shall contain the gpios used as R/B pins. + +see Documentation/devicetree/mtd/nand.txt for generic bindings. + + +Examples: +nfc: nand@01c03000 { + compatible = "allwinner,sun4i-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <0 37 1>; + clocks = <&ahb_gates 13>, <&nand_clk>; + clock-names = "ahb_clk", "sclk"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; + status = "okay"; + + nand@0 { + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "soft_bch"; + onfi,nand-timing-mode = <4>; + }; +};