From patchwork Fri Jan 24 21:32:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Inamdar X-Patchwork-Id: 314089 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 7E7072C00A2 for ; Sat, 25 Jan 2014 08:34:37 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753217AbaAXVeM (ORCPT ); Fri, 24 Jan 2014 16:34:12 -0500 Received: from exprod5og105.obsmtp.com ([64.18.0.180]:58147 "HELO exprod5og105.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1753210AbaAXVdo (ORCPT ); Fri, 24 Jan 2014 16:33:44 -0500 Received: from mail-pa0-f51.google.com ([209.85.220.51]) (using TLSv1) by exprod5ob105.postini.com ([64.18.4.12]) with SMTP ID DSNKUuLcOD/adlGUxsZyY+TAQA0OspbcQYWQ@postini.com; Fri, 24 Jan 2014 13:33:44 PST Received: by mail-pa0-f51.google.com with SMTP id ld10so3748221pab.10 for ; Fri, 24 Jan 2014 13:33:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aNu5qFrJuv+1UHWf+da2tzM/B4pwzi/TxI4GUlz6GRk=; b=IgUsqXxI0Nb1PBXMKsAUXaKe0HpAYBfyHwFCdUAnyVsmwlB8LNp7fqCK+Nn+w4ywKa yDareNarD2pTVixEbo1e/TGUWZU2ItoYRgJJpwJvWMY+igbMa7aAXxSlvAbe/Ddq1PV2 jikY5+vnLkHCYL9rjNwPXqwcIiQxZSOtMl3J1tub9Py0FVjNbLA+D5dyUyufG/T1DFmg TqG63AZrB45I7hn/A5/b88DJb0JT77n9iACRDI0SbnJOpKqWypQZnO5BTieRMI3vEe2Q AjnaeM2bzSy6IHv6vQhzXwaG+6OPSg75gOnTA0yEoE+n97BhwZEp1mk+duhA05k0H8Ml eKcg== X-Gm-Message-State: ALoCoQnnOWnDKrGyfZidyHisZSdwyt7IcogeCu4eTBpR9ZFlh4BAJMOHLyCZcwlCS9WOZjCU6qFZdKIrTiRn9R7dNvGJBiJPtBF9HmG22G6bm9Z7AgcOHVK/Bp7VEz6PruQiu8XQItL8LeiMiV2DUmxaQVMr/or3EYJkTlQkXekxy9BCg3LjMzo= X-Received: by 10.68.218.3 with SMTP id pc3mr16512407pbc.71.1390599223792; Fri, 24 Jan 2014 13:33:43 -0800 (PST) X-Received: by 10.68.218.3 with SMTP id pc3mr16512397pbc.71.1390599223718; Fri, 24 Jan 2014 13:33:43 -0800 (PST) Received: from amcclab-ThinkStation-E30.amcc.com (63-147-59-2.dia.static.qwest.net. [63.147.59.2]) by mx.google.com with ESMTPSA id xu8sm16140245pab.0.2014.01.24.13.33.42 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 24 Jan 2014 13:33:43 -0800 (PST) From: Tanmay Inamdar To: Bjorn Helgaas , Arnd Bergmann , Jason Gunthorpe , Grant Likely , Rob Herring , Catalin Marinas , Rob Landley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, patches@apm.com, jcm@redhat.com, Tanmay Inamdar Subject: [RFC PATCH V3 3/4] dt-bindings: pci: xgene pcie device tree bindings Date: Fri, 24 Jan 2014 13:32:47 -0800 Message-Id: <1390599168-13150-4-git-send-email-tinamdar@apm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1390599168-13150-1-git-send-email-tinamdar@apm.com> References: <1390599168-13150-1-git-send-email-tinamdar@apm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the bindings for X-Gene PCIe driver. The driver resides under 'drivers/pci/host/pci-xgene.c' file. Signed-off-by: Tanmay Inamdar --- .../devicetree/bindings/pci/xgene-pci.txt | 52 ++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xgene-pci.txt diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt new file mode 100644 index 0000000..60e4a54 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xgene-pci.txt @@ -0,0 +1,52 @@ +* AppliedMicro X-Gene PCIe interface + +Required properties: +- device_type: set to "pci" +- compatible: should contain "xgene,pcie" to identify the core. +- reg: A list of physical base address and length for each set of controller + registers. Must contain an entry for each entry in the reg-names + property. +- reg-names: Must include the following entries: + "csr": controller configuration registers. + "cfg": pcie configuration space registers. +- #address-cells: set to <3> +- #size-cells: set to <2> +- ranges: ranges for the outbound memory, I/O regions. +- dma-ranges: ranges for the inbound memory regions. +- #interrupt-cells: set to <1> +- interrupt-map-mask and interrupt-map: standard PCI properties + to define the mapping of the PCIe interface to interrupt + numbers. +- clocks: from common clock binding: handle to pci clock. + +Optional properties: +- status: Either "ok" or "disabled". + +Example: + +SoC specific DT Entry: + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ + 0xe0 0xd0000000 0x0 0x00200000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xe0 0x00000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x10000000 0xe0 0x10000000 0x00 0x80000000>; /* mem */ + dma-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; + clocks = <&pcie0clk 0>; + }; + +Board specific DT Entry: + &pcie0 { + status = "ok"; + };