From patchwork Tue Jan 7 11:41:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 307616 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C60DB2C00D1 for ; Tue, 7 Jan 2014 22:45:26 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751095AbaAGLpZ (ORCPT ); Tue, 7 Jan 2014 06:45:25 -0500 Received: from mail-pd0-f169.google.com ([209.85.192.169]:33128 "EHLO mail-pd0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751175AbaAGLpY (ORCPT ); Tue, 7 Jan 2014 06:45:24 -0500 Received: by mail-pd0-f169.google.com with SMTP id v10so268310pde.14 for ; Tue, 07 Jan 2014 03:45:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=iNpkh5xihJOvb6SMkH/4uDq0JF50CK/Fxp/PTWpNwew=; b=SzrNtajQrbVC4UXk2X7cMbAWw6oANoMZjGvo1PWKQsegObieMa/KG1em5QWAapKQhb o+mk9qpnizlpa4KXFp9UznLM02+Fec2i4FQnZ5a5DX0zHiGZnMQYZRy8i39DvNGMxsg1 bwcKiN64KQ755X3xVMBWMbsnKpMALZ08BS7gE1OBnP/rWG3bUrfZpLrzJboPj5Dsg1Ug DILUshMKCUlILbWV4/Akh9hR3W1NKURsLadJ2L3CkbiGgPSz4MeQz7gIvYp8YPYIBPDC p06vZhPpOfOzrusCdEXZHdHh6nR2y5BNu7+lvcr0ZClyNoRmy02sd0Bqp2hu1+Uklen0 qBsg== X-Gm-Message-State: ALoCoQmKzoKmriaai23AgE/hlOlIXAEYeTG/HPvQCOKxyLYxmYNWToBsdbXnOWrdJ8AVFUqaEKO6 X-Received: by 10.68.143.100 with SMTP id sd4mr119088675pbb.0.1389095123991; Tue, 07 Jan 2014 03:45:23 -0800 (PST) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id pa1sm177329749pac.17.2014.01.07.03.45.21 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 07 Jan 2014 03:45:23 -0800 (PST) From: Tushar Behera To: linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: linux@arm.linux.org.uk, arnd@arndb.de Subject: [PATCH] ARM: cache-l2x0: Parse properties from DT for PL310 cache controller Date: Tue, 7 Jan 2014 17:11:28 +0530 Message-Id: <1389094888-24348-1-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Parsed auxiliary control properties for PL310 cache controller. Signed-off-by: Tushar Behera --- These properties are set for Exynos4 platform. If we can pass these properties through device tree for Exynos4, then we can remove the hard-coded L2_AUX_VAL. Documentation/devicetree/bindings/arm/l2cc.txt | 10 ++++++++++ arch/arm/include/asm/hardware/cache-l2x0.h | 1 + arch/arm/mm/cache-l2x0.c | 25 ++++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index b513cb8..213546d 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -44,6 +44,16 @@ Optional properties: - cache-id-part: cache id part number to be used if it is not present on hardware - wt-override: If present then L2 is forced to Write through mode +- arm,early-write: If present then BRSEP mode (early write response) is enabled. +- arm,data-prefetch: If present then data prefetching is enabled. +- arm,instruction-prefetch: If present then instruction prefetching is enabled. +- arm,ns-interrupt-access: If present then interrupt mask and interrupt clear + registers can be read or modified in both secure or non-secure accesses. +- arm,ns-lockdown: If present then non-secure accesses can write to lockdown + register. +- arm,share-override: If present then shared attribute is ignored internally. +- arm,full-line-of-zero: If present then 'full line of write zero' behaviour is + enabled. Example: diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 6795ff7..aefdec0 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -78,6 +78,7 @@ #define L2X0_CACHE_ID_RTL_R3P2 0x8 #define L2X0_AUX_CTRL_MASK 0xc0000fff +#define L2X0_AUX_CTRL_FULL_LINE_OF_ZERO_SHIFT 0 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 7abde2c..03357f1 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -705,6 +705,7 @@ static void __init pl310_of_setup(const struct device_node *np, u32 data[3] = { 0, 0, 0 }; u32 tag[3] = { 0, 0, 0 }; u32 filter[2] = { 0, 0 }; + u32 val = 0; of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); if (tag[0] && tag[1] && tag[2]) @@ -731,6 +732,30 @@ static void __init pl310_of_setup(const struct device_node *np, writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN, l2x0_base + L2X0_ADDR_FILTER_START); } + + if (of_find_property(np, "arm,early-write", NULL)) + val |= BIT(L2X0_AUX_CTRL_EARLY_BRESP_SHIFT); + + if (of_find_property(np, "arm,instruction-prefetch", NULL)) + val |= BIT(L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT); + + if (of_find_property(np, "arm,data-prefetch", NULL)) + val |= BIT(L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT); + + if (of_find_property(np, "arm,ns-interrupt-access", NULL)) + val |= BIT(L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT); + + if (of_find_property(np, "arm,ns-lockdown", NULL)) + val |= BIT(L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT); + + if (of_find_property(np, "arm,share-override", NULL)) + val |= BIT(L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT); + + if (of_find_property(np, "arm,full-line-of-zero", NULL)) + val |= BIT(L2X0_AUX_CTRL_FULL_LINE_OF_ZERO_SHIFT); + + *aux_val |= val; + *aux_mask &= ~val; } static void __init pl310_save(void)