From patchwork Thu Dec 19 14:16:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 303140 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 7879E2C00AF for ; Thu, 19 Dec 2013 13:19:15 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752218Ab3LSCTN (ORCPT ); Wed, 18 Dec 2013 21:19:13 -0500 Received: from mail-db9lp0250.outbound.messaging.microsoft.com ([213.199.154.250]:48243 "EHLO db9outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752187Ab3LSCTK (ORCPT ); Wed, 18 Dec 2013 21:19:10 -0500 Received: from mail80-db9-R.bigfish.com (10.174.16.254) by DB9EHSOBE033.bigfish.com (10.174.14.96) with Microsoft SMTP Server id 14.1.225.22; Thu, 19 Dec 2013 02:19:09 +0000 Received: from mail80-db9 (localhost [127.0.0.1]) by mail80-db9-R.bigfish.com (Postfix) with ESMTP id 6F855340117; Thu, 19 Dec 2013 02:19:09 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 6 X-BigFish: VS6(zz853kzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6h1082kzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received: from mail80-db9 (localhost.localdomain [127.0.0.1]) by mail80-db9 (MessageSwitch) id 1387419546739992_8093; Thu, 19 Dec 2013 02:19:06 +0000 (UTC) Received: from DB9EHSMHS008.bigfish.com (unknown [10.174.16.228]) by mail80-db9.bigfish.com (Postfix) with ESMTP id A257DE0046; Thu, 19 Dec 2013 02:19:06 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB9EHSMHS008.bigfish.com (10.174.14.18) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 19 Dec 2013 02:19:06 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.158.2; Thu, 19 Dec 2013 02:19:06 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id rBJ2Iuuk015876; Wed, 18 Dec 2013 19:19:04 -0700 From: Anson Huang To: , , CC: , , , Subject: [PATCH V4 3/3] cpufreq: imx6: Add device tree binding document Date: Thu, 19 Dec 2013 09:16:49 -0500 Message-ID: <1387462609-13013-3-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1387462609-13013-1-git-send-email-b20788@freescale.com> References: <1387462609-13013-1-git-send-email-b20788@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This device tree binding document describes the imx6 cpufreq DT bindings. This document lists all required and optional properties for imx6 cpufreq. Signed-off-by: Anson Huang --- .../devicetree/bindings/cpufreq/cpufreq-imx6.txt | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt new file mode 100644 index 0000000..a14b895 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt @@ -0,0 +1,56 @@ +i.MX6 cpufreq driver +------------------- + +i.MX6 SoC cpufreq driver for CPU frequency scaling. + +This binding doc defines properties that must be put in the /cpus/cpu@0 node, +please refer to Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt +for detail. + +Required properties: +- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt + for details. +- clocks: Specify clocks that need to be used when cpu frequency is scaled, + refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for + details. +- clock-names: List of clock input name strings sorted in the same order as the + clocks property, refer to Documentation/devicetree/bindings/clock/clock-bindings.txt + for details. +- xxx-supply: Input voltage supply regulator, refer to + Documentation/devicetree/bindings/regulator/regulator.txt for details. + arm-supply: regulator node supplying arm. + pu-supply: regulator node supplying pu. + soc-supply: regulator node supplying soc. + +Optional properties: +- fsl,soc-operating-points: Specify vddsoc/pu voltage settings that must + go with cpu0's operating-points. +- clock-latency: Specify the possible maximum transition latency for clock, + in unit of nanoseconds. + +Examples: + + cpu@0 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 792000 1150000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks 104>, <&clks 6>, <&clks 16>, + <&clks 17>, <&clks 170>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + };