From patchwork Tue Dec 17 22:08:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 302073 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5EB802C00A5 for ; Tue, 17 Dec 2013 21:10:56 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751274Ab3LQKKz (ORCPT ); Tue, 17 Dec 2013 05:10:55 -0500 Received: from mail-db9lp0251.outbound.messaging.microsoft.com ([213.199.154.251]:28186 "EHLO db9outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750972Ab3LQKKx (ORCPT ); Tue, 17 Dec 2013 05:10:53 -0500 Received: from mail78-db9-R.bigfish.com (10.174.16.234) by DB9EHSOBE035.bigfish.com (10.174.14.98) with Microsoft SMTP Server id 14.1.225.22; Tue, 17 Dec 2013 10:10:51 +0000 Received: from mail78-db9 (localhost [127.0.0.1]) by mail78-db9-R.bigfish.com (Postfix) with ESMTP id D5F1A1E0204; Tue, 17 Dec 2013 10:10:51 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6h1082kzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received: from mail78-db9 (localhost.localdomain [127.0.0.1]) by mail78-db9 (MessageSwitch) id 1387275045925341_28680; Tue, 17 Dec 2013 10:10:45 +0000 (UTC) Received: from DB9EHSMHS011.bigfish.com (unknown [10.174.16.240]) by mail78-db9.bigfish.com (Postfix) with ESMTP id 434692200FE; Tue, 17 Dec 2013 10:10:44 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB9EHSMHS011.bigfish.com (10.174.14.21) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 17 Dec 2013 10:10:43 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.158.2; Tue, 17 Dec 2013 10:10:42 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id rBHAAcJA002729; Tue, 17 Dec 2013 03:10:39 -0700 From: Anson Huang To: , , CC: , , , Subject: [PATCH V2 1/2] ARM: imx: add vddsoc/pu setpoint info into dts Date: Tue, 17 Dec 2013 17:08:21 -0500 Message-ID: <1387318102-11070-1-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org i.MX6Q needs to update vddarm, vddsoc/pu regulators when cpu freq is changed, each setpoint has different voltage, so we need to pass vddarm, vddsoc/pu's freq-voltage info from dts together. Signed-off-by: Anson Huang --- .../devicetree/bindings/cpufreq/cpufreq-imx6.txt | 39 ++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 7 ++++ 2 files changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt new file mode 100644 index 0000000..0c71dbf --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt @@ -0,0 +1,39 @@ +i.MX6 cpufreq driver +------------------- + +i.MX6 SoC cpufreq driver for CPU frequency scaling. + +Optional properties: +-fsl,soc-operating-points: Specify vddsoc/pu voltage settings that must + go with cpu0's operating-points. + +Examples: + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 792000 1150000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks 104>, <&clks 6>, <&clks 16>, + <&clks 17>, <&clks 170>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index e7e8332..021e0cb 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -30,6 +30,13 @@ 792000 1150000 396000 975000 >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks 104>, <&clks 6>, <&clks 16>, <&clks 17>, <&clks 170>;