From patchwork Fri Dec 13 01:23:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Chen X-Patchwork-Id: 300845 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D0BBF2C00A7 for ; Fri, 13 Dec 2013 12:56:09 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752043Ab3LMB4I (ORCPT ); Thu, 12 Dec 2013 20:56:08 -0500 Received: from co1ehsobe005.messaging.microsoft.com ([216.32.180.188]:31754 "EHLO co1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752010Ab3LMB4G (ORCPT ); Thu, 12 Dec 2013 20:56:06 -0500 Received: from mail120-co1-R.bigfish.com (10.243.78.244) by CO1EHSOBE041.bigfish.com (10.243.66.106) with Microsoft SMTP Server id 14.1.225.22; Fri, 13 Dec 2013 01:56:05 +0000 Received: from mail120-co1 (localhost [127.0.0.1]) by mail120-co1-R.bigfish.com (Postfix) with ESMTP id 1FBCCAC01EE; Fri, 13 Dec 2013 01:56:05 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received: from mail120-co1 (localhost.localdomain [127.0.0.1]) by mail120-co1 (MessageSwitch) id 138689976383094_6881; Fri, 13 Dec 2013 01:56:03 +0000 (UTC) Received: from CO1EHSMHS032.bigfish.com (unknown [10.243.78.247]) by mail120-co1.bigfish.com (Postfix) with ESMTP id 07482B00048; Fri, 13 Dec 2013 01:56:03 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS032.bigfish.com (10.243.66.42) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 13 Dec 2013 01:56:02 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.3.158.2; Fri, 13 Dec 2013 01:56:01 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id rBD1tWvu026858; Thu, 12 Dec 2013 18:55:56 -0700 From: Peter Chen To: , , , CC: , , , , , , , , , , , Subject: [PATCH v6 04/15] usb: doc: phy-mxs: update binding for adding anatop phandle Date: Fri, 13 Dec 2013 09:23:34 +0800 Message-ID: <1386897825-6130-5-git-send-email-peter.chen@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1386897825-6130-1-git-send-email-peter.chen@freescale.com> References: <1386897825-6130-1-git-send-email-peter.chen@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add anatop phandle which is used to access anatop registers to control PHY's power and other USB operations. Signed-off-by: Peter Chen --- Documentation/devicetree/bindings/usb/mxs-phy.txt | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/mxs-phy.txt b/Documentation/devicetree/bindings/usb/mxs-phy.txt index d850e55..059536c 100644 --- a/Documentation/devicetree/bindings/usb/mxs-phy.txt +++ b/Documentation/devicetree/bindings/usb/mxs-phy.txt @@ -5,10 +5,12 @@ Required properties: for imx6dq and imx6dl, "fsl,imx6sl-usbphy" for imx6sl - reg: Should contain registers location and length - interrupts: Should contain phy interrupt +- fsl,anatop: phandle for anatop register, it is only for imx6 SoC series Example: usbphy1: usbphy@020c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; + fsl,anatop = <&anatop>; };