From patchwork Tue Nov 26 07:01:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loc Ho X-Patchwork-Id: 294229 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id DF6B12C00B3 for ; Tue, 26 Nov 2013 18:01:50 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754503Ab3KZHBt (ORCPT ); Tue, 26 Nov 2013 02:01:49 -0500 Received: from exprod5og104.obsmtp.com ([64.18.0.178]:43233 "HELO exprod5og104.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1754526Ab3KZHBs (ORCPT ); Tue, 26 Nov 2013 02:01:48 -0500 Received: from mail-pb0-f50.google.com ([209.85.160.50]) (using TLSv1) by exprod5ob104.postini.com ([64.18.4.12]) with SMTP ID DSNKUpRHXHcmCT39ulR/BIZ0ZKRM1PopOYVZ@postini.com; Mon, 25 Nov 2013 23:01:48 PST Received: by mail-pb0-f50.google.com with SMTP id rr13so7480560pbb.9 for ; Mon, 25 Nov 2013 23:01:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BciXu5Z/Q1MBmENKEYqVN7KT+IQJLQq2lmVayMGX4og=; b=bk3ZXcMQtKk49clUYWKD8n1fs1bFV/EgYpVW5K/KGm39QZVCDL+rsTtrxrd8sw16Lc U4qQyZfxqC/3t13RGvXQc3jUTTNykFn+4kFW1oMgl/rzYcDVKX8UGWWPstxxkOJW0xxu BSXYbc5xzZxAnCjl/F37vC1PxxicWR3vDfQGW6ctYj71er4cdtDBnbHZkcKZ+sdp8zxT ceOYiy6QAc/g7eDaljkB96I4McMOHNYe6Tb+M9IbyGJsuVasdfIcDdEXegje68c9bkcn Of60jSWhccsSCM8uChvn51HGpXH5TielJozPTCfJnNKHSMZsEh+L88+6y874QOPVgSQ4 JTEA== X-Gm-Message-State: ALoCoQlHehbKPdLsR/LXxNUlJNAdXfklvk+r1S2mwGKhvrULYa00F6N6r5NDuB7QRYdddCaep9ptTGsC30BHK0GjBksgisHT3DMB71rKCZRxpaPaOvq5Yg9Pq659YWMx1rsDld/k6Df66iUQA66W+Qzni/9RFZVHK3pQXpy9O+q+G68rLnUrqr8= X-Received: by 10.66.145.40 with SMTP id sr8mr32384349pab.60.1385449307038; Mon, 25 Nov 2013 23:01:47 -0800 (PST) X-Received: by 10.66.145.40 with SMTP id sr8mr32384334pab.60.1385449306972; Mon, 25 Nov 2013 23:01:46 -0800 (PST) Received: from localhost ([198.137.200.11]) by mx.google.com with ESMTPSA id hw10sm78191463pbc.24.2013.11.25.23.01.46 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 25 Nov 2013 23:01:46 -0800 (PST) From: Loc Ho To: olof@lixom.net, tj@kernel.org, arnd@arndb.de Cc: linux-scsi@vger.kernel.org, linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jcm@redhat.com, patches@apm.com, Loc Ho , Tuan Phan , Suman Tripathi Subject: [PATCH v5 2/4] Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding Date: Tue, 26 Nov 2013 00:01:23 -0700 Message-Id: <1385449285-30764-3-git-send-email-lho@apm.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1385449285-30764-2-git-send-email-lho@apm.com> References: <1385449285-30764-1-git-send-email-lho@apm.com> <1385449285-30764-2-git-send-email-lho@apm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Documentation: Add documentation for APM X-Gene SoC SATA host controller DTS binding Signed-off-by: Loc Ho Signed-off-by: Tuan Phan Signed-off-by: Suman Tripathi --- .../devicetree/bindings/ata/apm-xgene.txt | 102 ++++++++++++++++++++ 1 files changed, 102 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt new file mode 100644 index 0000000..879eee7 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt @@ -0,0 +1,102 @@ +* APM X-Gene 6.0 Gb/s SATA host controller and clock nodes + +SATA host controller nodes are defined to describe on-chip Serial ATA +controllers. Each SATA controller (pair of ports) have its own node. Its +corresponding clock nodes are shown below. + +Required properties: +- compatible : Shall be "apm,xgene-ahci-sgmii" if mux'ed with SGMII + or "apm,xgene-ahci-pcie" if mux'ed with PCIe. +- reg : First memory resource shall be the AHCI memory + resource. + Second memory resource shall be the host controller + memory resource. +- interrupt-parent : Interrupt controller. +- interrupts : Interrupt mapping for SATA host controller IRQ. +- clocks : Reference to the clock entry. +- phys : PHY reference with parameter 0. +- phy-names : Name of the PHY. Shall be "sata-6g". + +Optional properties: +- status : Shall be "ok" if enabled or "na" if disabled. + Default is "ok". + +Example: + sata01clk: sata01clk@1f21c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "sata01clk"; + reg = <0x0 0x1f21c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata01clk"; + status = "ok"; + csr-offset = <0x4>; + csr-mask = <0x3f>; + enable-offset = <0x0>; + enable-mask = <0x3f>; + }; + + sata23clk: sata23clk@1f22c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "sata23clk"; + reg = <0x0 0x1f22c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata23clk"; + csr-offset = <0x4>; + csr-mask = <0x3f>; + enable-offset = <0x0>; + enable-mask = <0x3f>; + }; + + sata45clk: sata45clk@1f23c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "sata45clk"; + reg = <0x0 0x1f23c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata45clk"; + csr-offset = <0x4>; + csr-mask = <0x3f>; + enable-offset = <0x0>; + enable-mask = <0x3f>; + }; + + sata1: sata@1a000000 { + compatible = "apm,xgene-ahci-sgmii"; + reg = <0x0 0x1a000000 0x0 0x1000>, + <0x0 0x1f210000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0x0 0x86 0x4>; + status = "disabled"; + clocks = <&sata01clk 0>; + phys = <&phy1 0>; + phy-names = "sata-6g"; + }; + + sata2: sata@1a400000 { + compatible = "apm,xgene-ahci-sgmii"; + reg = <0x0 0x1a400000 0x0 0x1000>, + <0x0 0x1f220000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0x0 0x87 0x4>; + status = "ok"; + clocks = <&sata23clk 0>; + phys = <&phy2 0>; + phy-names = "sata-6g"; + }; + + sata3: sata@1a800000 { + compatible = "apm,xgene-ahci-pcie"; + reg = <0x0 0x1a800000 0x0 0x1000>, + <0x0 0x1f230000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0x0 0x88 0x4>; + status = "ok"; + clocks = <&sata45clk 0>; + phys = <&phy3 0>; + phy-names = "sata-6g"; + };