From patchwork Mon Nov 25 08:54:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shirish S X-Patchwork-Id: 293859 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A8F412C054E for ; Mon, 25 Nov 2013 19:57:01 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753848Ab3KYI47 (ORCPT ); Mon, 25 Nov 2013 03:56:59 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:27142 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752853Ab3KYI4I (ORCPT ); Mon, 25 Nov 2013 03:56:08 -0500 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MWT00GQEA504TD0@mailout3.samsung.com> for devicetree@vger.kernel.org; Mon, 25 Nov 2013 17:55:48 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.125]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 18.77.18301.49013925; Mon, 25 Nov 2013 17:55:48 +0900 (KST) X-AuditID: cbfee68e-b7f7e6d00000477d-ac-529310942e67 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 4A.D7.32308.39013925; Mon, 25 Nov 2013 17:55:47 +0900 (KST) Received: from rahulsharma-ubuntu.sisodomain.com ([107.108.83.245]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MWT005PRA4NVTA1@mmp1.samsung.com>; Mon, 25 Nov 2013 17:55:47 +0900 (KST) From: Shirish S To: dri-devel@lists.freedesktop.org, inki.dae@samsung.com, devicetree@vger.kernel.org, mark.rutland@arm.com Cc: airlied@redhat.com, shirish@chromium.org, Shirish S Subject: [PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings Date: Mon, 25 Nov 2013 14:24:39 +0530 Message-id: <1385369679-4337-6-git-send-email-s.shirish@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1385369679-4337-1-git-send-email-s.shirish@samsung.com> References: <1385369679-4337-1-git-send-email-s.shirish@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRmVeSWpSXmKPExsWyRsSkVneKwOQgg4urOS2u3lrAZDH/yDlW iytf37NZTLo/gcVi6fWLTBbTZm9ktGjacZDNgd1jzbw1jB6zGy6yeNzvPs7k8X7fVTaPvi2r GD0+b5ILYIvisklJzcksSy3St0vgyuicdZy54KZ+xbt7L5kaGBvVuhg5OSQETCSmvtjJCGGL SVy4t56ti5GLQ0hgKaNE096NrDBFV2bdZYVILGKUWLLyNguEM4lJonvBJ2aQKjYBdYmLk1eD 2SICuRKHZ0HEmQX8Jf7smMsCYgsLeEvM2zsbbB2LgKpEa/M8dhCbV8BFYsXpHqB6DqBtChJz JtmAhDkFXCUez3oMNkYIqGT+4Z+MIHslBBaxS1w+9IYFYo6AxLfJh1ggemUlNh1ghjhaUuLg ihssExiFFzAyrGIUTS1ILihOSi8y0itOzC0uzUvXS87P3cQIDPjT/5717WC8ecD6EGMy0LiJ zFKiyfnAiMkriTc0NjOyMDUxNTYytzQjTVhJnHfRw6QgIYH0xJLU7NTUgtSi+KLSnNTiQ4xM HJxSDYxpct1JZovni3p4bnU87xp/parFJe27a1DH2xuzSzxiL11r1xe99vzttAlTl36aE3Hl fvLFpxcV13H8fTnxear7blFxyx/vt/4QVX7uyMFmHDkz3XzSgXZ7lp1mgow9S9bfmte64ZAs /0H3dWm2ocr3W9INvjX//rbj45KqJ3cVGibMYzkw4ckpJZbijERDLeai4kQAhpoHYo4CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBIsWRmVeSWpSXmKPExsVy+t9jAd3JApODDHbst7G4emsBk8X8I+dY La58fc9mMen+BBaLpdcvMllMm72R0aJpx0E2B3aPNfPWMHrMbrjI4nG/+ziTx/t9V9k8+ras YvT4vEkugC2qgdEmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE31VbJxSdA 1y0zB+gYJYWyxJxSoFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYGaCBhDWNG56zjzAU39Sve 3XvJ1MDYqNbFyMkhIWAicWXWXVYIW0ziwr31bF2MXBxCAosYJZasvM0C4Uxikuhe8IkZpIpN QF3i4uTVYLaIQK7E4VkQcWYBf4k/O+aygNjCAt4S8/bOZgSxWQRUJVqb57GD2LwCLhIrTvcA 1XMAbVOQmDPJBiTMKeAq8XjWY7AxQkAl8w//ZJzAyLuAkWEVo2hqQXJBcVJ6rqFecWJucWle ul5yfu4mRnA8PZPawbiyweIQowAHoxIPr0XlpCAh1sSy4srcQ4wSHMxKIrx76oBCvCmJlVWp RfnxRaU5qcWHGJOBjprILCWanA+M9bySeENjE3NTY1NLEwsTM0vShJXEeQ+0WgcKCaQnlqRm p6YWpBbBbGHi4JRqYFzivaHy3BKeDwUm657fnesUHf+S8Udyly2j7aKSo3n16k+suN7cYxHf 8+VGbCbbnT/3nPd5OMXMyPx5IW4ig+9nJZtV0ZLuPIfnZfy7uMzpudy5sv/9V5xMJvFpac2u tyvU2qyyITd82dKuW8HzzGpdS5vXMKXfVYzNclm0i4ttyQN7VefkOUosxRmJhlrMRcWJABBN cPfrAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds dt support to hdmiphy config settings as it is board specific and depends on the signal pattern of board. Signed-off-by: Shirish S --- .../devicetree/bindings/video/exynos_hdmi.txt | 31 ++++++++ drivers/gpu/drm/exynos/exynos_hdmi.c | 77 +++++++++++++++++++- 2 files changed, 104 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index 323983b..6eeb333 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt @@ -13,6 +13,30 @@ Required properties: b) pin number within the gpio controller. c) optional flags and pull up/down. +- hdmiphy-configs: following information about the hdmiphy config settings. + a) "config: config" specifies the phy configuration settings, + where 'N' denotes the number of configuration, since every + pixel clock can have its unique configuration. + "pixel-clock" specifies the pixel clock + "conifig-de-emphasis-level" provides fine control of TMDS data + pre emphasis, below shown is example for + data de-emphasis register at address 0x145D0040. + hdmiphy@38[16] for bits[3:0] permitted values are in + the range of 760 mVdiff to 1400 mVdiff at 20mVdiff + increments for every LSB + hdmiphy@38[16] for bits[7:4] permitted values are in + the range of 0dB to -7.45dB at increments of -0.45dB + for every LSB. + "config-clock-level" provides fine control of TMDS data + amplitude for each channel, + for example if 0x145D005C is the address of clock level + register then, + hdmiphy@38[23] for bits [1:0] permitted values are in + the range of 0 mVdiff & 60 mVdiff for each channel at + increments 20 mVdiff of amplitude levels for every LSB, + hdmiphy@38[23] for bits [7:3] permitted values are in + the range of 790 and 1430 mV at 20mV increments for + every LSB. Example: hdmi { @@ -20,4 +44,11 @@ Example: reg = <0x14530000 0x100000>; interrupts = <0 95 0>; hpd-gpio = <&gpx3 7 1>; + hdmiphy-configs { + config0: config0 { + pixel-clock = <25200000>; + config-de-emphasis-level = /bits/ 8 <0x26>; + config-clock-level = /bits/ 8 < 0x66>; + }; + } }; diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 32ce9a6..5f599e3 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -197,6 +197,9 @@ struct hdmi_context { struct hdmi_resources res; + struct hdmiphy_config *confs; + int nr_confs; + int hpd_gpio; enum hdmi_type type; @@ -256,7 +259,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { }, }; -static const struct hdmiphy_config hdmiphy_v14_configs[] = { +static struct hdmiphy_config hdmiphy_v14_configs[] = { { .pixel_clock = 25200000, .conf = { @@ -785,8 +788,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) confs = hdmiphy_v13_configs; count = ARRAY_SIZE(hdmiphy_v13_configs); } else if (hdata->type == HDMI_TYPE14) { - confs = hdmiphy_v14_configs; - count = ARRAY_SIZE(hdmiphy_v14_configs); + confs = hdata->confs; + count = hdata->nr_confs; } else return -EINVAL; @@ -1415,7 +1418,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) if (hdata->type == HDMI_TYPE13) hdmiphy_data = hdmiphy_v13_configs[i].conf; else - hdmiphy_data = hdmiphy_v14_configs[i].conf; + hdmiphy_data = hdata->confs[i].conf; memcpy(buffer, hdmiphy_data, 32); ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32); @@ -1894,6 +1897,63 @@ fail: return -ENODEV; } +static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev, + struct hdmi_context *hdata) +{ + struct device *dev = &pdev->dev; + struct device_node *dev_np = dev->of_node; + struct device_node *phy_conf, *cfg_np; + int i, pixel_clock = 0; + + /* Initialize with default config */ + hdata->confs = hdmiphy_v14_configs; + hdata->nr_confs = ARRAY_SIZE(hdmiphy_v14_configs); + + phy_conf = of_find_node_by_name(dev_np, "hdmiphy-configs"); + if (phy_conf == NULL) { + hdata->nr_confs = ARRAY_SIZE(hdmiphy_v14_configs); + DRM_ERROR("Did not find hdmiphy-configs node\n"); + return -ENODEV; + } + + for_each_child_of_node(phy_conf, cfg_np) { + if (!of_find_property(cfg_np, "pixel-clock", NULL)) + continue; + + if (of_property_read_u32(cfg_np, "pixel-clock", + &pixel_clock, 1)) { + DRM_ERROR("Failed to get pixel clock\n"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(hdmiphy_v14_configs); i++) { + if (hdata->confs[i].pixel_clock == pixel_clock) + /* Update the data de-emphasis and data level */ + if (of_property_read_u8_array(cfg_np, + "config-de-emphasis-level", + &hdata->confs[i].conf[16], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + if (of_property_read_u8_array(cfg_np, + "config-de-emphasis-level", + &hdata->confs[i].conf[16], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + /* Update the clock level diff */ + if (of_property_read_u8_array(cfg_np, + "config-clock-level", + &hdata->confs[i].conf[23], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + } + } + return 0; + +} + static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata (struct device *dev) { @@ -2024,6 +2084,15 @@ static int hdmi_probe(struct platform_device *pdev) goto err_hdmiphy; } + /* get hdmiphy confs */ + if (hdata->type == HDMI_TYPE14) { + ret = drm_hdmi_dt_parse_phy_conf(pdev, hdata); + if (ret) { + DRM_ERROR("failed to get user defined config,will use + default configs, eye diagram tests may fail\n"); + } + } + hdmi_display.dev = dev; exynos_drm_display_register(&hdmi_display);