From patchwork Mon Nov 11 09:41:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tang yuantian X-Patchwork-Id: 290226 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 042B32C00C7 for ; Mon, 11 Nov 2013 21:26:35 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753002Ab3KKK0e (ORCPT ); Mon, 11 Nov 2013 05:26:34 -0500 Received: from va3ehsobe001.messaging.microsoft.com ([216.32.180.11]:44842 "EHLO va3outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752994Ab3KKK0d (ORCPT ); Mon, 11 Nov 2013 05:26:33 -0500 Received: from mail72-va3-R.bigfish.com (10.7.14.248) by VA3EHSOBE004.bigfish.com (10.7.40.24) with Microsoft SMTP Server id 14.1.225.22; Mon, 11 Nov 2013 10:26:33 +0000 Received: from mail72-va3 (localhost [127.0.0.1]) by mail72-va3-R.bigfish.com (Postfix) with ESMTP id 1F94F2400F2; Mon, 11 Nov 2013 10:26:33 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h1155h) Received: from mail72-va3 (localhost.localdomain [127.0.0.1]) by mail72-va3 (MessageSwitch) id 1384165590710677_19748; Mon, 11 Nov 2013 10:26:30 +0000 (UTC) Received: from VA3EHSMHS009.bigfish.com (unknown [10.7.14.226]) by mail72-va3.bigfish.com (Postfix) with ESMTP id A7FDC10005D; Mon, 11 Nov 2013 10:26:30 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS009.bigfish.com (10.7.99.19) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 11 Nov 2013 10:26:30 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Mon, 11 Nov 2013 10:26:29 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id rABAQJBH009889; Mon, 11 Nov 2013 03:26:21 -0700 From: To: CC: , , , , , Tang Yuantian , Tang Yuantian , Li Yang Subject: [PATCH v6] clk: corenet: Adds the clock binding Date: Mon, 11 Nov 2013 17:41:46 +0800 Message-ID: <1384162906-30730-1-git-send-email-Yuantian.Tang@freescale.com> X-Mailer: git-send-email 1.8.0 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tang Yuantian Adds the clock bindings for Freescale PowerPC CoreNet platforms Signed-off-by: Tang Yuantian Signed-off-by: Li Yang --- v6: - splited the previous patch into 2 parts, one is for binding(this one), the other is for DTS modification(will submit once this gets accepted) - fixed typo - refined #clock-cells and clock-output-names properties - removed fixed-clock compatible string v5: - refine the binding document - update the compatible string v4: - add binding document - update compatible string - update the reg property v3: - fix typo v2: - add t4240, b4420, b4860 support - remove pll/4 clock from p2041, p3041 and p5020 board .../devicetree/bindings/clock/corenet-clock.txt | 123 +++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/corenet-clock.txt diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt b/Documentation/devicetree/bindings/clock/corenet-clock.txt new file mode 100644 index 0000000..6a4e15d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt @@ -0,0 +1,123 @@ +* Clock Block on Freescale CoreNet Platforms + +Freescale CoreNet chips take primary clocking input from the external +SYSCLK signal. The SYSCLK input (frequency) is multiplied using +multiple phase locked loops (PLL) to create a variety of frequencies +which can then be passed to a variety of internal logic, including +cores and peripheral IP blocks. +Please refer to the Reference Manual for details. + +1. Clock Block Binding + +Required properties: +- compatible: Should include one or more of the following: + * "fsl,-clockgen": for chip specific clock block, here chip + could be but not limited to one of the: p2041, p3041, p4080, + p5020, p5040, t4240, b4420, b4860 + * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks + * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks + Notes that "fsl,qoriq-clockgen-1.0" and "fsl,qoriq-clockgen-2.0" + cannot be included simultaneously. +- reg: Offset and length of the clock register set + +Recommended properties: +- ranges: Allows valid translation between child's address space and + parent's. Must be present if the device has sub-nodes. +- #address-cells: Specifies the number of cells used to represent + physical base addresses. Must be present if the device has + sub-nodes and set to 1 if present +- #size-cells: Specifies the number of cells used to represent + the size of an address. Must be present if the device has + sub-nodes and set to 1 if present + +2. Clock Provider/Consumer Binding + +Most of the bindings are from the common clock binding[1]. + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : Should include one of the following: + * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) + * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) + * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) + * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) + * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0) + * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0) +- #clock-cells: From common clock binding; indicates the number of + output clock. 0 is for "fsl,qoriq-sysclk-[1,2].0" and + "fsl,qoriq-core-mux-[1,2].0"; 1 for "fsl,qoriq-core-pll-[1,2].0". + If #clock-cells has a value of 1, its clock consumer should specify + the desired clock by having the clock ID in its "clocks" phandle + cell. The following is a full list IDs: + * 0 - equal to the PLL frequency + * 1 - equal to the PLL frequency divided by 2 + * 2 - equal to the PLL frequency divided by 4 + +Recommended properties: +- clocks: Should be the phandle of input parent clock +- clock-names: From common clock binding, indicates the clock name +- clock-output-names: From common clock binding, indicates the names of + output clocks +- reg: Should be the offset and length of clock block base address. + The length should be 4. + +Example for clock block and clock provider: +/ { + clockgen: global-utilities@e1000 { + compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; + ranges = <0x0 0xe1000 0x1000>; + reg = <0xe1000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + sysclk: sysclk { + #clock-cells = <0>; + compatible = "fsl,qoriq-sysclk-1.0"; + clock-output-names = "sysclk"; + } + + pll0: pll0@800 { + #clock-cells = <1>; + reg = <0x800 0x4>; + compatible = "fsl,qoriq-core-pll-1.0"; + clocks = <&sysclk>; + clock-output-names = "pll0", "pll0-div2"; + }; + + pll1: pll1@820 { + #clock-cells = <1>; + reg = <0x820 0x4>; + compatible = "fsl,qoriq-core-pll-1.0"; + clocks = <&sysclk>; + clock-output-names = "pll1", "pll1-div2"; + }; + + mux0: mux0@0 { + #clock-cells = <0>; + reg = <0x0 0x4>; + compatible = "fsl,qoriq-core-mux-1.0"; + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; + clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; + clock-output-names = "cmux0"; + }; + + mux1: mux1@20 { + #clock-cells = <0>; + reg = <0x20 0x4>; + compatible = "fsl,qoriq-core-mux-1.0"; + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; + clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; + clock-output-names = "cmux1"; + }; + }; + } + +Example for clock consumer: + +/ { + cpu0: PowerPC,e5500@0 { + ... + clocks = <&mux0>; + ... + }; + }