From patchwork Thu Nov 7 15:17:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 289384 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E0FD32C00D1 for ; Fri, 8 Nov 2013 02:17:53 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752413Ab3KGPRw (ORCPT ); Thu, 7 Nov 2013 10:17:52 -0500 Received: from top.free-electrons.com ([176.31.233.9]:51864 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752191Ab3KGPRv (ORCPT ); Thu, 7 Nov 2013 10:17:51 -0500 Received: by mail.free-electrons.com (Postfix, from userid 106) id 96ED5837; Thu, 7 Nov 2013 16:18:03 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.3.2 Received: from localhost.localdomain (unknown [190.2.98.212]) by mail.free-electrons.com (Postfix) with ESMTPA id 513A1827; Thu, 7 Nov 2013 16:17:49 +0100 (CET) From: Ezequiel Garcia To: , , Cc: Lior Amsalem , Tawfik Bayouk , Thomas Petazzoni , Gregory Clement , Brian Norris , Huang Shijie , Willy Tarreau , Daniel Mack , Jason Cooper , Ezequiel Garcia Subject: [PATCH v4 02/31] ARM: mvebu: Add Core Divider clock device-tree binding Date: Thu, 7 Nov 2013 12:17:06 -0300 Message-Id: <1383837455-30721-3-git-send-email-ezequiel.garcia@free-electrons.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1383837455-30721-1-git-send-email-ezequiel.garcia@free-electrons.com> References: <1383837455-30721-1-git-send-email-ezequiel.garcia@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Armada 370/XP SoCs have a Core Divider clock providing several clocks. For now, only the NAND clock is supported. Reviewed-by: Gregory CLEMENT Signed-off-by: Ezequiel Garcia --- .../devicetree/bindings/clock/mvebu-corediv-clock.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt new file mode 100644 index 0000000..c62391f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt @@ -0,0 +1,19 @@ +* Core Divider Clock bindings for Marvell MVEBU SoCs + +The following is a list of provided IDs and clock names on Armada 370/XP: + 0 = nand (NAND clock) + +Required properties: +- compatible : must be "marvell,armada-370-corediv-clock" +- reg : must be the register address of Core Divider control register +- #clock-cells : from common clock binding; shall be set to 1 +- clocks : must be set to the parent's phandle + +Example: + +corediv_clk: corediv-clocks@18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; + #clock-cells = <1>; + clocks = <&pll>; +};