From patchwork Mon Dec 12 10:56:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 704976 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tcft71n5qz9sfH for ; Mon, 12 Dec 2016 21:57:03 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="FNYonC+m"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932460AbcLLK4s (ORCPT ); Mon, 12 Dec 2016 05:56:48 -0500 Received: from mail-pg0-f51.google.com ([74.125.83.51]:34672 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932640AbcLLK4o (ORCPT ); Mon, 12 Dec 2016 05:56:44 -0500 Received: by mail-pg0-f51.google.com with SMTP id x23so34392985pgx.1 for ; Mon, 12 Dec 2016 02:56:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=HdiQtcziwnd3wTv/okfZePrjQ+d7QPhRu1z8GorTXoA=; b=FNYonC+mUPvjra9H3AaPUQjkRocM13sCXfv020A0volcaa1O7YLVYJoiH9VO/3kKqo f329b7olbjZzNdTIYoOf3KxYa+fgdffPqA7YR3DQMOEjZlH2LF6lxHxXjUJyO6cBxF9L AmmkdEo2FmzOtvLpfbsjvwmthoK1SH40mwlas= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=HdiQtcziwnd3wTv/okfZePrjQ+d7QPhRu1z8GorTXoA=; b=jG8TeUFafT9gDz6lxJBJWFmGxK1bZuOGX0pqwyeK5tmCA6W61pY02mfbLzlmKH8KAc uMZr8A9HLw9+le15EDrZbwZcf4SUjS4KA9PsR8fHKoTgmtvHF679UgvUILYvX/dE5fZc jSCVor3yuKxY3xeNmI4ELG2tFxDySG7QV4lwmv7NSap9VQU44WBLQhX6mk3t3iIY4+E0 eGTF+KhAsUTbtVlKHDRusqLwaM0IdjA2sGoi70TxraxR7PWnKbB407iC35Rg/rNoeGli RcVZruim5W0ldf5hy0vMbDTQ5ZgWPwnAZOkiO50GLV624DhxbP9NVQuvECuAPPPfb/1L 69DA== X-Gm-Message-State: AKaTC03egqjyNb4YEseKRA9mb3tLs45DLA69FKL41wyCtal7EVOeuHxuZx8sbX10C56rabXx X-Received: by 10.84.214.150 with SMTP id j22mr134590682pli.81.1481540198360; Mon, 12 Dec 2016 02:56:38 -0800 (PST) Received: from localhost ([122.172.43.83]) by smtp.gmail.com with ESMTPSA id z9sm75500400pfd.29.2016.12.12.02.56.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Dec 2016 02:56:37 -0800 (PST) From: Viresh Kumar To: Rafael Wysocki , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Vincent Guittot , Rob Herring , Mark Rutland , Kevin Hilman , Ulf Hansson , Lina Iyer , devicetree@vger.kernel.org, Nayak Rajendra , Viresh Kumar Subject: [PATCH V2 2/2] PM / OPP: Introduce domain-performance-state binding to OPP nodes Date: Mon, 12 Dec 2016 16:26:19 +0530 Message-Id: <0ace336cf1041611fa561a79b38e879d6816b5d0.1481539827.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.7.1.410.g6faf27b In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some platforms have the capability to configure the performance state of their Power Domains. The performance levels are represented by positive integer values, a lower value represents lower performance state. If the consumers don't need the capability of switching to different domain performance states at runtime, then they can simply define their required domain performance state in their nodes directly. But if the device needs the capability of switching to different domain performance states, as they may need to support different clock rates, then the per OPP node can be used to contain that information. This patch introduces the domain-performance-state (already defined by Power Domain bindings) to the per OPP node. Signed-off-by: Viresh Kumar --- Documentation/devicetree/bindings/opp/opp.txt | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt index 9f5ca4457b5f..43eba7c9fc58 100644 --- a/Documentation/devicetree/bindings/opp/opp.txt +++ b/Documentation/devicetree/bindings/opp/opp.txt @@ -154,6 +154,9 @@ properties. - status: Marks the node enabled/disabled. +- domain-performance-state: A phandle of a Performance state node as defined by + ../power/power_domain.txt binding document. + Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. / { @@ -528,3 +531,59 @@ Example 5: opp-supported-hw }; }; }; + +Example 7: domain-Performance-state: +(example: For 1GHz require domain state 1 and for 1.1 & 1.2 GHz require state 2) + +/ { + foo_domain: power-controller@12340000 { + compatible = "foo,power-controller"; + reg = <0x12340000 0x1000>; + #power-domain-cells = <0>; + domain-performance-states = <&domain_perf_states>; + }; + + domain_perf_states: performance_states { + compatible = "domain-performance-state"; + domain_perf_state1: pstate@1 { + performance-level = <1>; + domain-microvolt = <970000 975000 985000>; + }; + domain_perf_state2: pstate@2 { + performance-level = <2>; + domain-microvolt = <1000000 1075000 1085000>; + }; + } + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&foo_domain>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + domain-performance-state = <&domain_perf_state1>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + domain-performance-state = <&domain_perf_state2>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + domain-performance-state = <&domain_perf_state2>; + }; + }; +};