| Message ID | cover.1632761067.git.hns@goldelico.com |
|---|---|
| Headers | show |
| Series | MIPS: JZ4780 and CI20 HDMI | expand |
Hi, On Mon, Sep 27, 2021 at 06:44:23PM +0200, H. Nikolaus Schaller wrote: > It appears that dw-hdmi plugin detection is not properly > propagated unless we call drm_kms_helper_hotplug_event(). > > Maybe drm_bridge_hpd_notify should have been setup to > call this. > > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > index f082e14320e1..edea04f80576 100644 > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > @@ -3018,6 +3018,8 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) > if (hdmi->bridge.dev) { > drm_helper_hpd_irq_event(hdmi->bridge.dev); > drm_bridge_hpd_notify(&hdmi->bridge, status); > + > + drm_kms_helper_hotplug_event(hdmi->bridge.dev); drm_kms_helper_hotplug_event is already called from drm_helper_hpd_irq_event Maxime
On Mon, Sep 27, 2021 at 06:44:24PM +0200, H. Nikolaus Schaller wrote: > From: Paul Boddie <paul@boddie.org.uk> > > A specialisation of the generic Synopsys HDMI driver is employed for JZ4780 > HDMI support. This requires a new driver, plus device tree and configuration > modifications. > > Signed-off-by: Paul Boddie <paul@boddie.org.uk> > Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > drivers/gpu/drm/ingenic/Kconfig | 9 ++ > drivers/gpu/drm/ingenic/Makefile | 1 + > drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 142 ++++++++++++++++++++++ > 3 files changed, 152 insertions(+) > create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c > > diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig > index 3b57f8be007c..4c7d311fbeff 100644 > --- a/drivers/gpu/drm/ingenic/Kconfig > +++ b/drivers/gpu/drm/ingenic/Kconfig > @@ -25,4 +25,13 @@ config DRM_INGENIC_IPU > > The Image Processing Unit (IPU) will appear as a second primary plane. > > +config DRM_INGENIC_DW_HDMI > + bool "Ingenic specific support for Synopsys DW HDMI" > + depends on MACH_JZ4780 > + select DRM_DW_HDMI > + help > + Choose this option to enable Synopsys DesignWare HDMI based driver. > + If you want to enable HDMI on Ingenic JZ4780 based SoC, you should > + select this option.. > + > endif > diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile > index d313326bdddb..3db9888a6c04 100644 > --- a/drivers/gpu/drm/ingenic/Makefile > +++ b/drivers/gpu/drm/ingenic/Makefile > @@ -1,3 +1,4 @@ > obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o > ingenic-drm-y = ingenic-drm-drv.o > ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o > +ingenic-drm-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o > diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c > new file mode 100644 > index 000000000000..dd9c94ae842e > --- /dev/null > +++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c > @@ -0,0 +1,142 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. > + * Copyright (C) 2019, 2020 Paul Boddie <paul@boddie.org.uk> > + * > + * Derived from dw_hdmi-imx.c with i.MX portions removed. > + * Probe and remove operations derived from rcar_dw_hdmi.c. > + */ > + > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > + > +#include <drm/bridge/dw_hdmi.h> > +#include <drm/drm_of.h> > +#include <drm/drm_print.h> > + > +static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = { > + { 45250000, { { 0x01e0, 0x0000 }, { 0x21e1, 0x0000 }, { 0x41e2, 0x0000 } } }, > + { 92500000, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, 0x0005 } } }, > + { 148500000, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, 0x000a } } }, > + { 216000000, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f } } }, > + { ~0UL, { { 0x0000, 0x0000 }, { 0x0000, 0x0000 }, { 0x0000, 0x0000 } } } > +}; > + > +static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = { > + /*pixelclk bpp8 bpp10 bpp12 */ > + { 54000000, { 0x091c, 0x091c, 0x06dc } }, > + { 58400000, { 0x091c, 0x06dc, 0x06dc } }, > + { 72000000, { 0x06dc, 0x06dc, 0x091c } }, > + { 74250000, { 0x06dc, 0x0b5c, 0x091c } }, > + { 118800000, { 0x091c, 0x091c, 0x06dc } }, > + { 216000000, { 0x06dc, 0x0b5c, 0x091c } }, > + { ~0UL, { 0x0000, 0x0000, 0x0000 } }, > +}; > + > +/* > + * Resistance term 133Ohm Cfg > + * PREEMP config 0.00 > + * TX/CK level 10 > + */ > +static const struct dw_hdmi_phy_config ingenic_phy_config[] = { > + /*pixelclk symbol term vlev */ > + { 216000000, 0x800d, 0x0005, 0x01ad}, > + { ~0UL, 0x0000, 0x0000, 0x0000} > +}; > + > +static enum drm_mode_status > +ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, > + const struct drm_display_info *info, > + const struct drm_display_mode *mode) > +{ > + if (mode->clock < 13500) > + return MODE_CLOCK_LOW; > + /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */ > + if (mode->clock > 216000) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} > + > +static bool > +ingenic_dw_hdmi_mode_fixup(struct drm_bridge *bridge, > + const struct drm_display_mode *mode, > + struct drm_display_mode *adjusted_mode) > +{ > + adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); > + adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); > + > + return true; > +} > + > +static const struct drm_bridge_timings ingenic_dw_hdmi_timings = { > + .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, > +}; > + > +static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = { > + .mpll_cfg = ingenic_mpll_cfg, > + .cur_ctr = ingenic_cur_ctr, > + .phy_config = ingenic_phy_config, > + .mode_valid = ingenic_dw_hdmi_mode_valid, > + .mode_fixup = ingenic_dw_hdmi_mode_fixup, > + .timings = &ingenic_dw_hdmi_timings, > + .output_port = 1, > +}; > + > +static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = { > + { .compatible = "ingenic,jz4780-dw-hdmi" }, > + { /* Sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids); > + > +static int ingenic_dw_hdmi_probe(struct platform_device *pdev) > +{ > + struct dw_hdmi *hdmi; > + struct regulator *regulator; > + int ret; > + > + hdmi = dw_hdmi_probe(pdev, &ingenic_dw_hdmi_plat_data); > + if (IS_ERR(hdmi)) > + return PTR_ERR(hdmi); > + > + platform_set_drvdata(pdev, hdmi); > + > + regulator = devm_regulator_get_optional(&pdev->dev, "hdmi-5v"); > + > + if (IS_ERR(regulator)) { > + ret = PTR_ERR(regulator); > + > + DRM_DEV_ERROR(&pdev->dev, "failed to get hpd regulator: %s (%d)\n", > + "hdmi-5v", ret); > + return ret; > + } This doesn't match your binding Maxime
> Am 27.09.2021 um 19:00 schrieb Maxime Ripard <maxime@cerno.tech>: > > Hi, > > On Mon, Sep 27, 2021 at 06:44:23PM +0200, H. Nikolaus Schaller wrote: >> It appears that dw-hdmi plugin detection is not properly >> propagated unless we call drm_kms_helper_hotplug_event(). >> >> Maybe drm_bridge_hpd_notify should have been setup to >> call this. >> >> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> >> --- >> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >> index f082e14320e1..edea04f80576 100644 >> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >> @@ -3018,6 +3018,8 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) >> if (hdmi->bridge.dev) { >> drm_helper_hpd_irq_event(hdmi->bridge.dev); >> drm_bridge_hpd_notify(&hdmi->bridge, status); >> + >> + drm_kms_helper_hotplug_event(hdmi->bridge.dev); > > drm_kms_helper_hotplug_event is already called from drm_helper_hpd_irq_event Ah, now I see. It should be called but is not for some unkown condition (poll disabled? changed = false?). It may also be a leftover from the attempt to make it work with the builtin dw-hdmi connector. Will check for v5. BR and thanks, Nikolaus
Hi Nikolaus / Paul, Le lun., sept. 27 2021 at 18:44:20 +0200, H. Nikolaus Schaller <hns@goldelico.com> a écrit : > From: Paul Boddie <paul@boddie.org.uk> > > Add support for the LCD controller present on JZ4780 SoCs. > This SoC uses 8-byte descriptors which extend the current > 4-byte descriptors used for other Ingenic SoCs. > > Tested on MIPS Creator CI20 board. > > Signed-off-by: Paul Boddie <paul@boddie.org.uk> > Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 85 > +++++++++++++++++++++-- > drivers/gpu/drm/ingenic/ingenic-drm.h | 42 +++++++++++ > 2 files changed, 122 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > index f73522bdacaa..e2df4b085905 100644 > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > @@ -6,6 +6,7 @@ > > #include "ingenic-drm.h" > > +#include <linux/bitfield.h> > #include <linux/component.h> > #include <linux/clk.h> > #include <linux/dma-mapping.h> > @@ -49,6 +50,11 @@ struct ingenic_dma_hwdesc { > u32 addr; > u32 id; > u32 cmd; > + /* extended hw descriptor for jz4780 */ > + u32 offsize; > + u32 pagewidth; > + u32 cpos; > + u32 dessize; > } __aligned(16); > > struct ingenic_dma_hwdescs { > @@ -60,9 +66,11 @@ struct jz_soc_info { > bool needs_dev_clk; > bool has_osd; > bool map_noncoherent; > + bool use_extended_hwdesc; > unsigned int max_width, max_height; > const u32 *formats_f0, *formats_f1; > unsigned int num_formats_f0, num_formats_f1; > + unsigned int max_reg; > }; > > struct ingenic_drm_private_state { > @@ -168,12 +176,11 @@ static bool ingenic_drm_writeable_reg(struct > device *dev, unsigned int reg) > } > } > > -static const struct regmap_config ingenic_drm_regmap_config = { > +static struct regmap_config ingenic_drm_regmap_config = { > .reg_bits = 32, > .val_bits = 32, > .reg_stride = 4, > > - .max_register = JZ_REG_LCD_SIZE1, > .writeable_reg = ingenic_drm_writeable_reg, > }; > > @@ -663,6 +670,37 @@ static void > ingenic_drm_plane_atomic_update(struct drm_plane *plane, > hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); > hwdesc->next = dma_hwdesc_addr(priv, next_id); > > + if (priv->soc_info->use_extended_hwdesc) { > + hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE; > + > + /* Extended 8-byte descriptor */ > + hwdesc->cpos = 0; > + hwdesc->offsize = 0; > + hwdesc->pagewidth = 0; > + > + switch (newstate->fb->format->format) { > + case DRM_FORMAT_XRGB1555: > + hwdesc->cpos |= JZ_LCD_CPOS_RGB555; > + fallthrough; > + case DRM_FORMAT_RGB565: > + hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16; > + break; > + case DRM_FORMAT_XRGB8888: > + hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24; > + break; > + } > + hwdesc->cpos |= JZ_LCD_CPOS_PREMULTIPLY_LCD | > + (JZ_LCD_CPOS_COEFFICIENT_1_ALPHA1 << > + JZ_LCD_CPOS_COEFFICIENT_OFFSET); > + > + hwdesc->dessize = > + (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) | > + FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK << > + JZ_LCD_DESSIZE_HEIGHT_OFFSET, height - 1) | > + FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK << > + JZ_LCD_DESSIZE_WIDTH_OFFSET, width - 1); > + } > + > if (drm_atomic_crtc_needs_modeset(crtc_state)) { > fourcc = newstate->fb->format->format; > > @@ -694,6 +732,10 @@ static void > ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, > | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; > } > > + /* set use of the 8-word descriptor and OSD foreground usage. */ > + if (priv->soc_info->use_extended_hwdesc) > + cfg |= JZ_LCD_CFG_DESCRIPTOR_8; > + > if (mode->flags & DRM_MODE_FLAG_NHSYNC) > cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; > if (mode->flags & DRM_MODE_FLAG_NVSYNC) > @@ -1010,6 +1052,7 @@ static int ingenic_drm_bind(struct device *dev, > bool has_components) > struct drm_encoder *encoder; > struct ingenic_drm_bridge *ib; > struct drm_device *drm; > + struct regmap_config regmap_config; > void __iomem *base; > long parent_rate; > unsigned int i, clone_mask = 0; > @@ -1063,8 +1106,10 @@ static int ingenic_drm_bind(struct device > *dev, bool has_components) > return PTR_ERR(base); > } > > + regmap_config = ingenic_drm_regmap_config; > + regmap_config.max_register = soc_info->max_reg; > priv->map = devm_regmap_init_mmio(dev, base, > - &ingenic_drm_regmap_config); > + ®map_config); Could you split the code that makes .max_reg configurable per-SoC into its own patch? > if (IS_ERR(priv->map)) { > dev_err(dev, "Failed to create regmap\n"); > return PTR_ERR(priv->map); > @@ -1274,7 +1319,7 @@ static int ingenic_drm_bind(struct device *dev, > bool has_components) > > /* Enable OSD if available */ > if (soc_info->has_osd) > - regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); > + regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); Why? > > mutex_init(&priv->clk_mutex); > priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; > @@ -1444,6 +1489,7 @@ static const struct jz_soc_info jz4740_soc_info > = { > .formats_f1 = jz4740_formats, > .num_formats_f1 = ARRAY_SIZE(jz4740_formats), > /* JZ4740 has only one plane */ > + .max_reg = JZ_REG_LCD_SIZE1, > }; > > static const struct jz_soc_info jz4725b_soc_info = { > @@ -1456,6 +1502,7 @@ static const struct jz_soc_info > jz4725b_soc_info = { > .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), > .formats_f0 = jz4725b_formats_f0, > .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), > + .max_reg = JZ_REG_LCD_SIZE1, > }; > > static const struct jz_soc_info jz4770_soc_info = { > @@ -1468,12 +1515,28 @@ static const struct jz_soc_info > jz4770_soc_info = { > .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), > .formats_f0 = jz4770_formats_f0, > .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), > + .max_reg = JZ_REG_LCD_SIZE1, > +}; > + > +static const struct jz_soc_info jz4780_soc_info = { > + .needs_dev_clk = true, > + .has_osd = true, > + .use_extended_hwdesc = true, > + .max_width = 4096, > + .max_height = 2048, > + /* REVISIT: do we support formats different from jz4770? */ > + .formats_f1 = jz4770_formats_f1, > + .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), > + .formats_f0 = jz4770_formats_f0, > + .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), > + .max_reg = JZ_REG_LCD_PCFG, > }; > > static const struct of_device_id ingenic_drm_of_match[] = { > { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, > { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, > { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, > + { .compatible = "ingenic,jz4780-lcd", .data = &jz4780_soc_info }, > { /* sentinel */ }, > }; > MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); > @@ -1492,10 +1555,16 @@ static int ingenic_drm_init(void) > { > int err; > > + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) { > + err = platform_driver_register(ingenic_dw_hdmi_driver_ptr); > + if (err) > + return err; > + } I don't see why you need to register the ingenic-dw-hdmi driver here. Just register it in the ingenic-dw-hdmi driver. Cheers, -Paul > + > if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { > err = platform_driver_register(ingenic_ipu_driver_ptr); > if (err) > - return err; > + goto err_hdmi_unreg; > } > > err = platform_driver_register(&ingenic_drm_driver); > @@ -1507,6 +1576,10 @@ static int ingenic_drm_init(void) > err_ipu_unreg: > if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) > platform_driver_unregister(ingenic_ipu_driver_ptr); > +err_hdmi_unreg: > + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) > + platform_driver_unregister(ingenic_dw_hdmi_driver_ptr); > + > return err; > } > module_init(ingenic_drm_init); > @@ -1515,6 +1588,8 @@ static void ingenic_drm_exit(void) > { > platform_driver_unregister(&ingenic_drm_driver); > > + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) > + platform_driver_unregister(ingenic_dw_hdmi_driver_ptr); > if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) > platform_driver_unregister(ingenic_ipu_driver_ptr); > } > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.h > b/drivers/gpu/drm/ingenic/ingenic-drm.h > index 22654ac1dde1..13dbc5d25c3b 100644 > --- a/drivers/gpu/drm/ingenic/ingenic-drm.h > +++ b/drivers/gpu/drm/ingenic/ingenic-drm.h > @@ -44,8 +44,11 @@ > #define JZ_REG_LCD_XYP1 0x124 > #define JZ_REG_LCD_SIZE0 0x128 > #define JZ_REG_LCD_SIZE1 0x12c > +#define JZ_REG_LCD_PCFG 0x2c0 > > #define JZ_LCD_CFG_SLCD BIT(31) > +#define JZ_LCD_CFG_DESCRIPTOR_8 BIT(28) > +#define JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN BIT(25) > #define JZ_LCD_CFG_PS_DISABLE BIT(23) > #define JZ_LCD_CFG_CLS_DISABLE BIT(22) > #define JZ_LCD_CFG_SPL_DISABLE BIT(21) > @@ -63,6 +66,7 @@ > #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) > #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) > #define JZ_LCD_CFG_18_BIT BIT(7) > +#define JZ_LCD_CFG_24_BIT BIT(6) > #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) > > #define JZ_LCD_CFG_MODE_GENERIC_16BIT 0 > @@ -132,6 +136,7 @@ > #define JZ_LCD_CMD_SOF_IRQ BIT(31) > #define JZ_LCD_CMD_EOF_IRQ BIT(30) > #define JZ_LCD_CMD_ENABLE_PAL BIT(28) > +#define JZ_LCD_CMD_FRM_ENABLE BIT(26) > > #define JZ_LCD_SYNC_MASK 0x3ff > > @@ -153,6 +158,7 @@ > #define JZ_LCD_RGBC_EVEN_BGR (0x5 << 0) > > #define JZ_LCD_OSDC_OSDEN BIT(0) > +#define JZ_LCD_OSDC_ALPHAEN BIT(2) > #define JZ_LCD_OSDC_F0EN BIT(3) > #define JZ_LCD_OSDC_F1EN BIT(4) > > @@ -176,6 +182,41 @@ > #define JZ_LCD_SIZE01_WIDTH_LSB 0 > #define JZ_LCD_SIZE01_HEIGHT_LSB 16 > > +#define JZ_LCD_DESSIZE_ALPHA_OFFSET 24 > +#define JZ_LCD_DESSIZE_HEIGHT_OFFSET 12 > +#define JZ_LCD_DESSIZE_WIDTH_OFFSET 0 > +#define JZ_LCD_DESSIZE_HEIGHT_MASK 0xfff > +#define JZ_LCD_DESSIZE_WIDTH_MASK 0xfff > + > +/* TODO: 4,5 and 7 match the above BPP */ > +#define JZ_LCD_CPOS_BPP_15_16 (4 << 27) > +#define JZ_LCD_CPOS_BPP_18_24 (5 << 27) > +#define JZ_LCD_CPOS_BPP_30 (7 << 27) > +#define JZ_LCD_CPOS_RGB555 BIT(30) > +#define JZ_LCD_CPOS_PREMULTIPLY_LCD BIT(26) > +#define JZ_LCD_CPOS_COEFFICIENT_OFFSET 24 > +#define JZ_LCD_CPOS_COEFFICIENT_0 0 > +#define JZ_LCD_CPOS_COEFFICIENT_1 1 > +#define JZ_LCD_CPOS_COEFFICIENT_ALPHA1 2 > +#define JZ_LCD_CPOS_COEFFICIENT_1_ALPHA1 3 > + > +#define JZ_LCD_RGBC_RGB_PADDING BIT(15) > +#define JZ_LCD_RGBC_RGB_PADDING_FIRST BIT(14) > +#define JZ_LCD_RGBC_422 BIT(8) > +#define JZ_LCD_RGBC_RGB_FORMAT_ENABLE BIT(7) > + > +#define JZ_LCD_PCFG_PRI_MODE BIT(31) > +#define JZ_LCD_PCFG_HP_BST_4 (0 << 28) > +#define JZ_LCD_PCFG_HP_BST_8 (1 << 28) > +#define JZ_LCD_PCFG_HP_BST_16 (2 << 28) > +#define JZ_LCD_PCFG_HP_BST_32 (3 << 28) > +#define JZ_LCD_PCFG_HP_BST_64 (4 << 28) > +#define JZ_LCD_PCFG_HP_BST_16_CONT (5 << 28) > +#define JZ_LCD_PCFG_HP_BST_DISABLE (7 << 28) > +#define JZ_LCD_PCFG_THRESHOLD2_OFFSET 18 > +#define JZ_LCD_PCFG_THRESHOLD1_OFFSET 9 > +#define JZ_LCD_PCFG_THRESHOLD0_OFFSET 0 > + > struct device; > struct drm_plane; > struct drm_plane_state; > @@ -187,5 +228,6 @@ void ingenic_drm_plane_disable(struct device > *dev, struct drm_plane *plane); > bool ingenic_drm_map_noncoherent(const struct device *dev); > > extern struct platform_driver *ingenic_ipu_driver_ptr; > +extern struct platform_driver *ingenic_dw_hdmi_driver_ptr; > > #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */ > -- > 2.31.1 >
Hi, Le lun., sept. 27 2021 at 18:44:28 +0200, H. Nikolaus Schaller <hns@goldelico.com> a écrit : > From: Paul Boddie <paul@boddie.org.uk> > > The jz4780 has some features which need initialization > according to the vendor kernel. > > Signed-off-by: Paul Boddie <paul@boddie.org.uk> > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 39 > +++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > index e2df4b085905..605549b316b5 100644 > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > @@ -66,6 +66,10 @@ struct jz_soc_info { > bool needs_dev_clk; > bool has_osd; > bool map_noncoherent; > + bool has_alpha; > + bool has_pcfg; > + bool has_recover; > + bool has_rgbc; > bool use_extended_hwdesc; > unsigned int max_width, max_height; > const u32 *formats_f0, *formats_f1; > @@ -732,6 +736,9 @@ static void > ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, > | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; > } > > + if (priv->soc_info->has_recover) > + cfg |= JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN; Did you actually test this? I know that in theory it sounds like something we'd want, but unless there is a proven use for it, it's better to keep it disabled. > + > /* set use of the 8-word descriptor and OSD foreground usage. */ > if (priv->soc_info->use_extended_hwdesc) > cfg |= JZ_LCD_CFG_DESCRIPTOR_8; > @@ -1321,6 +1328,25 @@ static int ingenic_drm_bind(struct device > *dev, bool has_components) > if (soc_info->has_osd) > regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); > > + if (soc_info->has_alpha) > + regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_ALPHAEN); I remember you saying that OSD mode was not yet working on the JZ4780. So I can't see how you could have tested this. > + > + /* Magic values from the vendor kernel for the priority thresholds. > */ > + if (soc_info->has_pcfg) > + regmap_write(priv->map, JZ_REG_LCD_PCFG, > + JZ_LCD_PCFG_PRI_MODE | > + JZ_LCD_PCFG_HP_BST_16 | > + (511 << JZ_LCD_PCFG_THRESHOLD2_OFFSET) | > + (400 << JZ_LCD_PCFG_THRESHOLD1_OFFSET) | > + (256 << JZ_LCD_PCFG_THRESHOLD0_OFFSET)); Unless you add a big comment that explains what these values do and why we do want them, I don't want magic values in here. The fact that the kernel vendor sets this doesn't mean it's needed and/or wanted. > + > + /* RGB output control may be superfluous. */ > + if (soc_info->has_rgbc) > + regmap_write(priv->map, JZ_REG_LCD_RGBC, > + JZ_LCD_RGBC_RGB_FORMAT_ENABLE | > + JZ_LCD_RGBC_ODD_RGB | > + JZ_LCD_RGBC_EVEN_RGB); ingenic-drm only supports RGB output right now, so I guess the RGB_FORMAT_ENABLE bit needs to be set in patch [2/10], otherwise patch [2/10] cannot state that it adds support for the JZ4780, if it doesn't actually work. The other two bits can be dropped, they are already set in ingenic_drm_encoder_atomic_mode_set(). > + > mutex_init(&priv->clk_mutex); > priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; > > @@ -1484,6 +1510,9 @@ static const struct jz_soc_info jz4740_soc_info > = { > .needs_dev_clk = true, > .has_osd = false, > .map_noncoherent = false, > + .has_pcfg = false, > + .has_recover = false, > + .has_rgbc = false, > .max_width = 800, > .max_height = 600, > .formats_f1 = jz4740_formats, > @@ -1496,6 +1525,9 @@ static const struct jz_soc_info > jz4725b_soc_info = { > .needs_dev_clk = false, > .has_osd = true, > .map_noncoherent = false, > + .has_pcfg = false, > + .has_recover = false, > + .has_rgbc = false, This is wrong, the JZ4725B and JZ4770 SoCs both have the RGBC register and the RECOVER bit. Cheers, -Paul > .max_width = 800, > .max_height = 600, > .formats_f1 = jz4725b_formats_f1, > @@ -1509,6 +1541,9 @@ static const struct jz_soc_info jz4770_soc_info > = { > .needs_dev_clk = false, > .has_osd = true, > .map_noncoherent = true, > + .has_pcfg = false, > + .has_recover = false, > + .has_rgbc = false, > .max_width = 1280, > .max_height = 720, > .formats_f1 = jz4770_formats_f1, > @@ -1521,6 +1556,10 @@ static const struct jz_soc_info > jz4770_soc_info = { > static const struct jz_soc_info jz4780_soc_info = { > .needs_dev_clk = true, > .has_osd = true, > + .has_alpha = true, > + .has_pcfg = true, > + .has_recover = true, > + .has_rgbc = true, > .use_extended_hwdesc = true, > .max_width = 4096, > .max_height = 2048, > -- > 2.31.1 >
Hi Paul, > Am 28.09.2021 um 11:58 schrieb Paul Cercueil <paul@crapouillou.net>: > > Hi, > > Le lun., sept. 27 2021 at 18:44:28 +0200, H. Nikolaus Schaller <hns@goldelico.com> a écrit : >> From: Paul Boddie <paul@boddie.org.uk> >> The jz4780 has some features which need initialization >> according to the vendor kernel. >> Signed-off-by: Paul Boddie <paul@boddie.org.uk> >> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> >> --- >> drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 39 +++++++++++++++++++++++ >> 1 file changed, 39 insertions(+) >> diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> index e2df4b085905..605549b316b5 100644 >> --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> @@ -66,6 +66,10 @@ struct jz_soc_info { >> bool needs_dev_clk; >> bool has_osd; >> bool map_noncoherent; >> + bool has_alpha; >> + bool has_pcfg; >> + bool has_recover; >> + bool has_rgbc; >> bool use_extended_hwdesc; >> unsigned int max_width, max_height; >> const u32 *formats_f0, *formats_f1; >> @@ -732,6 +736,9 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, >> | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; >> } >> + if (priv->soc_info->has_recover) >> + cfg |= JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN; > > Did you actually test this? I know that in theory it sounds like something we'd want, but unless there is a proven use for it, it's better to keep it disabled. > >> + >> /* set use of the 8-word descriptor and OSD foreground usage. */ >> if (priv->soc_info->use_extended_hwdesc) >> cfg |= JZ_LCD_CFG_DESCRIPTOR_8; >> @@ -1321,6 +1328,25 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) >> if (soc_info->has_osd) >> regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); >> + if (soc_info->has_alpha) >> + regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_ALPHAEN); > > I remember you saying that OSD mode was not yet working on the JZ4780. So I can't see how you could have tested this. Basically this is all stuff from the vendor kernel under the assumption that they know better than everyone of us. On the other hand this whole patch is sort of optional and we know that the basic milestone to get HDMI working is reached without it. So if you prefer we can drop it for the moment in v5 and leave it for further analysis later. > >> + >> + /* Magic values from the vendor kernel for the priority thresholds. */ >> + if (soc_info->has_pcfg) >> + regmap_write(priv->map, JZ_REG_LCD_PCFG, >> + JZ_LCD_PCFG_PRI_MODE | >> + JZ_LCD_PCFG_HP_BST_16 | >> + (511 << JZ_LCD_PCFG_THRESHOLD2_OFFSET) | >> + (400 << JZ_LCD_PCFG_THRESHOLD1_OFFSET) | >> + (256 << JZ_LCD_PCFG_THRESHOLD0_OFFSET)); > > Unless you add a big comment that explains what these values do and why we do want them, I don't want magic values in here. The fact that the kernel vendor sets this doesn't mean it's needed and/or wanted. Well, who has a contact within Ingenic? > >> + >> + /* RGB output control may be superfluous. */ >> + if (soc_info->has_rgbc) >> + regmap_write(priv->map, JZ_REG_LCD_RGBC, >> + JZ_LCD_RGBC_RGB_FORMAT_ENABLE | >> + JZ_LCD_RGBC_ODD_RGB | >> + JZ_LCD_RGBC_EVEN_RGB); > > ingenic-drm only supports RGB output right now, so I guess the RGB_FORMAT_ENABLE bit needs to be set in patch [2/10], otherwise patch [2/10] cannot state that it adds support for the JZ4780, if it doesn't actually work. > > The other two bits can be dropped, they are already set in ingenic_drm_encoder_atomic_mode_set(). Ok. > >> + >> mutex_init(&priv->clk_mutex); >> priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; >> @@ -1484,6 +1510,9 @@ static const struct jz_soc_info jz4740_soc_info = { >> .needs_dev_clk = true, >> .has_osd = false, >> .map_noncoherent = false, >> + .has_pcfg = false, >> + .has_recover = false, >> + .has_rgbc = false, >> .max_width = 800, >> .max_height = 600, >> .formats_f1 = jz4740_formats, >> @@ -1496,6 +1525,9 @@ static const struct jz_soc_info jz4725b_soc_info = { >> .needs_dev_clk = false, >> .has_osd = true, >> .map_noncoherent = false, >> + .has_pcfg = false, >> + .has_recover = false, >> + .has_rgbc = false, > > This is wrong, the JZ4725B and JZ4770 SoCs both have the RGBC register and the RECOVER bit. Ok, good to know! Will change. BR and thanks, Nikolaus > > Cheers, > -Paul > >> .max_width = 800, >> .max_height = 600, >> .formats_f1 = jz4725b_formats_f1, >> @@ -1509,6 +1541,9 @@ static const struct jz_soc_info jz4770_soc_info = { >> .needs_dev_clk = false, >> .has_osd = true, >> .map_noncoherent = true, >> + .has_pcfg = false, >> + .has_recover = false, >> + .has_rgbc = false, >> .max_width = 1280, >> .max_height = 720, >> .formats_f1 = jz4770_formats_f1, >> @@ -1521,6 +1556,10 @@ static const struct jz_soc_info jz4770_soc_info = { >> static const struct jz_soc_info jz4780_soc_info = { >> .needs_dev_clk = true, >> .has_osd = true, >> + .has_alpha = true, >> + .has_pcfg = true, >> + .has_recover = true, >> + .has_rgbc = true, >> .use_extended_hwdesc = true, >> .max_width = 4096, >> .max_height = 2048, >> -- >> 2.31.1
Hi, > Am 28.09.2021 um 11:35 schrieb Paul Cercueil <paul@crapouillou.net>: > > Hi Nikolaus / Paul, > > Le lun., sept. 27 2021 at 18:44:20 +0200, H. Nikolaus Schaller <hns@goldelico.com> a écrit : >> From: Paul Boddie <paul@boddie.org.uk> >> Add support for the LCD controller present on JZ4780 SoCs. >> This SoC uses 8-byte descriptors which extend the current >> 4-byte descriptors used for other Ingenic SoCs. >> Tested on MIPS Creator CI20 board. >> Signed-off-by: Paul Boddie <paul@boddie.org.uk> >> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> >> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> >> --- >> drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 85 +++++++++++++++++++++-- >> drivers/gpu/drm/ingenic/ingenic-drm.h | 42 +++++++++++ >> 2 files changed, 122 insertions(+), 5 deletions(-) >> diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> index f73522bdacaa..e2df4b085905 100644 >> --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> @@ -6,6 +6,7 @@ >> #include "ingenic-drm.h" >> +#include <linux/bitfield.h> >> #include <linux/component.h> >> #include <linux/clk.h> >> #include <linux/dma-mapping.h> >> @@ -49,6 +50,11 @@ struct ingenic_dma_hwdesc { >> u32 addr; >> u32 id; >> u32 cmd; >> + /* extended hw descriptor for jz4780 */ >> + u32 offsize; >> + u32 pagewidth; >> + u32 cpos; >> + u32 dessize; >> } __aligned(16); >> struct ingenic_dma_hwdescs { >> @@ -60,9 +66,11 @@ struct jz_soc_info { >> bool needs_dev_clk; >> bool has_osd; >> bool map_noncoherent; >> + bool use_extended_hwdesc; >> unsigned int max_width, max_height; >> const u32 *formats_f0, *formats_f1; >> unsigned int num_formats_f0, num_formats_f1; >> + unsigned int max_reg; >> }; >> struct ingenic_drm_private_state { >> @@ -168,12 +176,11 @@ static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) >> } >> } >> -static const struct regmap_config ingenic_drm_regmap_config = { >> +static struct regmap_config ingenic_drm_regmap_config = { >> .reg_bits = 32, >> .val_bits = 32, >> .reg_stride = 4, >> - .max_register = JZ_REG_LCD_SIZE1, >> .writeable_reg = ingenic_drm_writeable_reg, >> }; >> @@ -663,6 +670,37 @@ static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, >> hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); >> hwdesc->next = dma_hwdesc_addr(priv, next_id); >> + if (priv->soc_info->use_extended_hwdesc) { >> + hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE; >> + >> + /* Extended 8-byte descriptor */ >> + hwdesc->cpos = 0; >> + hwdesc->offsize = 0; >> + hwdesc->pagewidth = 0; >> + >> + switch (newstate->fb->format->format) { >> + case DRM_FORMAT_XRGB1555: >> + hwdesc->cpos |= JZ_LCD_CPOS_RGB555; >> + fallthrough; >> + case DRM_FORMAT_RGB565: >> + hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16; >> + break; >> + case DRM_FORMAT_XRGB8888: >> + hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24; >> + break; >> + } >> + hwdesc->cpos |= JZ_LCD_CPOS_PREMULTIPLY_LCD | >> + (JZ_LCD_CPOS_COEFFICIENT_1_ALPHA1 << >> + JZ_LCD_CPOS_COEFFICIENT_OFFSET); >> + >> + hwdesc->dessize = >> + (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) | >> + FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK << >> + JZ_LCD_DESSIZE_HEIGHT_OFFSET, height - 1) | >> + FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK << >> + JZ_LCD_DESSIZE_WIDTH_OFFSET, width - 1); >> + } >> + >> if (drm_atomic_crtc_needs_modeset(crtc_state)) { >> fourcc = newstate->fb->format->format; >> @@ -694,6 +732,10 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, >> | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; >> } >> + /* set use of the 8-word descriptor and OSD foreground usage. */ >> + if (priv->soc_info->use_extended_hwdesc) >> + cfg |= JZ_LCD_CFG_DESCRIPTOR_8; >> + >> if (mode->flags & DRM_MODE_FLAG_NHSYNC) >> cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; >> if (mode->flags & DRM_MODE_FLAG_NVSYNC) >> @@ -1010,6 +1052,7 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) >> struct drm_encoder *encoder; >> struct ingenic_drm_bridge *ib; >> struct drm_device *drm; >> + struct regmap_config regmap_config; >> void __iomem *base; >> long parent_rate; >> unsigned int i, clone_mask = 0; >> @@ -1063,8 +1106,10 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) >> return PTR_ERR(base); >> } >> + regmap_config = ingenic_drm_regmap_config; >> + regmap_config.max_register = soc_info->max_reg; >> priv->map = devm_regmap_init_mmio(dev, base, >> - &ingenic_drm_regmap_config); >> + ®map_config); > > Could you split the code that makes .max_reg configurable per-SoC into its own patch? Yes. > >> if (IS_ERR(priv->map)) { >> dev_err(dev, "Failed to create regmap\n"); >> return PTR_ERR(priv->map); >> @@ -1274,7 +1319,7 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) >> /* Enable OSD if available */ >> if (soc_info->has_osd) >> - regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); >> + regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); > > Why? If I remember we should not assume that all others bits in JZ_REG_LCD_OSDC can be safely overwritten by 0, although their reset state is 0 as well. These are several alpha-blending bits and interrupt masks in the same register. Apparently only in jz4780. > >> mutex_init(&priv->clk_mutex); >> priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; >> @@ -1444,6 +1489,7 @@ static const struct jz_soc_info jz4740_soc_info = { >> .formats_f1 = jz4740_formats, >> .num_formats_f1 = ARRAY_SIZE(jz4740_formats), >> /* JZ4740 has only one plane */ >> + .max_reg = JZ_REG_LCD_SIZE1, >> }; >> static const struct jz_soc_info jz4725b_soc_info = { >> @@ -1456,6 +1502,7 @@ static const struct jz_soc_info jz4725b_soc_info = { >> .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), >> .formats_f0 = jz4725b_formats_f0, >> .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), >> + .max_reg = JZ_REG_LCD_SIZE1, >> }; >> static const struct jz_soc_info jz4770_soc_info = { >> @@ -1468,12 +1515,28 @@ static const struct jz_soc_info jz4770_soc_info = { >> .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), >> .formats_f0 = jz4770_formats_f0, >> .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), >> + .max_reg = JZ_REG_LCD_SIZE1, >> +}; >> + >> +static const struct jz_soc_info jz4780_soc_info = { >> + .needs_dev_clk = true, >> + .has_osd = true, >> + .use_extended_hwdesc = true, >> + .max_width = 4096, >> + .max_height = 2048, >> + /* REVISIT: do we support formats different from jz4770? */ >> + .formats_f1 = jz4770_formats_f1, >> + .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), >> + .formats_f0 = jz4770_formats_f0, >> + .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), >> + .max_reg = JZ_REG_LCD_PCFG, >> }; >> static const struct of_device_id ingenic_drm_of_match[] = { >> { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, >> { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, >> { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, >> + { .compatible = "ingenic,jz4780-lcd", .data = &jz4780_soc_info }, >> { /* sentinel */ }, >> }; >> MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); >> @@ -1492,10 +1555,16 @@ static int ingenic_drm_init(void) >> { >> int err; >> + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) { >> + err = platform_driver_register(ingenic_dw_hdmi_driver_ptr); >> + if (err) >> + return err; >> + } > > I don't see why you need to register the ingenic-dw-hdmi driver here. Just register it in the ingenic-dw-hdmi driver. Ok, I never though about this (as the code was not from me). We apparently just followed the IPU code pattern (learning by example). It indeed looks not necessary and would also avoid the ingenic_dw_hdmi_driver_ptr dependency. But: what is ingenic_ipu_driver_ptr then good for? If we can get rid of this as well, we can drop patch 1/10 ("drm/ingenic: Fix drm_init error path if IPU was registered") completely. > > Cheers, > -Paul > BR, Nikolaus
> Am 28.09.2021 um 12:06 schrieb H. Nikolaus Schaller <hns@goldelico.com>: > >>> >>> + >>> + /* RGB output control may be superfluous. */ >>> + if (soc_info->has_rgbc) >>> + regmap_write(priv->map, JZ_REG_LCD_RGBC, >>> + JZ_LCD_RGBC_RGB_FORMAT_ENABLE | >>> + JZ_LCD_RGBC_ODD_RGB | >>> + JZ_LCD_RGBC_EVEN_RGB); >> >> ingenic-drm only supports RGB output right now, so I guess the RGB_FORMAT_ENABLE bit needs to be set in patch [2/10], otherwise patch [2/10] cannot state that it adds support for the JZ4780, if it doesn't actually work. interestingly it works without setting anything in this register. >> >> The other two bits can be dropped, they are already set in ingenic_drm_encoder_atomic_mode_set(). > > Ok. Setting it manually doesn't change anything visible: root@letux:~# devmem2 0x13050090 /dev/mem opened. Memory mapped at address 0x77e14000. Value at address 0x13050090 (0x77e14090): 0x0 root@letux:~# devmem2 0x13050090 w 0x80 /dev/mem opened. Memory mapped at address 0x77e38000. Value at address 0x13050090 (0x77e38090): 0x0 Written 0x80; readback 0x80 root@letux:~# Same for 0x130A0090. Maybe this lcdc register is not used at all - at least for HDMI? So I'd suggest to drop this whole patch from v5. BR and thanks, Nikolaus
Hi Paul, > Am 28.09.2021 um 12:21 schrieb H. Nikolaus Schaller <hns@goldelico.com>: > >>> @@ -1492,10 +1555,16 @@ static int ingenic_drm_init(void) >>> { >>> int err; >>> + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) { >>> + err = platform_driver_register(ingenic_dw_hdmi_driver_ptr); >>> + if (err) >>> + return err; >>> + } >> >> I don't see why you need to register the ingenic-dw-hdmi driver here. Just register it in the ingenic-dw-hdmi driver. > > Ok, I never though about this (as the code was not from me). We apparently just followed the IPU code pattern (learning by example). > > It indeed looks not necessary and would also avoid the ingenic_dw_hdmi_driver_ptr dependency. > > But: what is ingenic_ipu_driver_ptr then good for? > > If we can get rid of this as well, we can drop patch 1/10 ("drm/ingenic: Fix drm_init error path if IPU was registered") completely. A quick test shows that it *is* required. At least if I configure everything as modules. But like you I can't explain why. Well, just a very rough idea (may be wrong): the bridge chain is not like an i2c bus and clients are not automatically loaded/probed if linked in the device tree. Therefore the consumer (ingenic_drm_drv) must register the "clients" like IPU and HDMI. BR, Nikolaus
On 27/09/2021 18:44, H. Nikolaus Schaller wrote: > From: Paul Boddie <paul@boddie.org.uk> > > A specialisation of the generic Synopsys HDMI driver is employed for JZ4780 > HDMI support. This requires a new driver, plus device tree and configuration > modifications. > > Signed-off-by: Paul Boddie <paul@boddie.org.uk> > Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > drivers/gpu/drm/ingenic/Kconfig | 9 ++ > drivers/gpu/drm/ingenic/Makefile | 1 + > drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 142 ++++++++++++++++++++++ > 3 files changed, 152 insertions(+) > create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c > > diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig > index 3b57f8be007c..4c7d311fbeff 100644 > --- a/drivers/gpu/drm/ingenic/Kconfig > +++ b/drivers/gpu/drm/ingenic/Kconfig > @@ -25,4 +25,13 @@ config DRM_INGENIC_IPU > > The Image Processing Unit (IPU) will appear as a second primary plane. > > +config DRM_INGENIC_DW_HDMI > + bool "Ingenic specific support for Synopsys DW HDMI" > + depends on MACH_JZ4780 > + select DRM_DW_HDMI > + help > + Choose this option to enable Synopsys DesignWare HDMI based driver. > + If you want to enable HDMI on Ingenic JZ4780 based SoC, you should > + select this option.. > + > endif > diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile > index d313326bdddb..3db9888a6c04 100644 > --- a/drivers/gpu/drm/ingenic/Makefile > +++ b/drivers/gpu/drm/ingenic/Makefile > @@ -1,3 +1,4 @@ > obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o > ingenic-drm-y = ingenic-drm-drv.o > ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o > +ingenic-drm-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o > diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c > new file mode 100644 > index 000000000000..dd9c94ae842e > --- /dev/null > +++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c > @@ -0,0 +1,142 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. > + * Copyright (C) 2019, 2020 Paul Boddie <paul@boddie.org.uk> > + * > + * Derived from dw_hdmi-imx.c with i.MX portions removed. > + * Probe and remove operations derived from rcar_dw_hdmi.c. > + */ > + > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > + > +#include <drm/bridge/dw_hdmi.h> > +#include <drm/drm_of.h> > +#include <drm/drm_print.h> > + > +static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = { > + { 45250000, { { 0x01e0, 0x0000 }, { 0x21e1, 0x0000 }, { 0x41e2, 0x0000 } } }, > + { 92500000, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, 0x0005 } } }, > + { 148500000, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, 0x000a } } }, > + { 216000000, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f } } }, > + { ~0UL, { { 0x0000, 0x0000 }, { 0x0000, 0x0000 }, { 0x0000, 0x0000 } } } > +}; > + > +static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = { > + /*pixelclk bpp8 bpp10 bpp12 */ > + { 54000000, { 0x091c, 0x091c, 0x06dc } }, > + { 58400000, { 0x091c, 0x06dc, 0x06dc } }, > + { 72000000, { 0x06dc, 0x06dc, 0x091c } }, > + { 74250000, { 0x06dc, 0x0b5c, 0x091c } }, > + { 118800000, { 0x091c, 0x091c, 0x06dc } }, > + { 216000000, { 0x06dc, 0x0b5c, 0x091c } }, > + { ~0UL, { 0x0000, 0x0000, 0x0000 } }, > +}; > + > +/* > + * Resistance term 133Ohm Cfg > + * PREEMP config 0.00 > + * TX/CK level 10 > + */ > +static const struct dw_hdmi_phy_config ingenic_phy_config[] = { > + /*pixelclk symbol term vlev */ > + { 216000000, 0x800d, 0x0005, 0x01ad}, > + { ~0UL, 0x0000, 0x0000, 0x0000} > +}; > + > +static enum drm_mode_status > +ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, > + const struct drm_display_info *info, > + const struct drm_display_mode *mode) > +{ > + if (mode->clock < 13500) > + return MODE_CLOCK_LOW; > + /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */ > + if (mode->clock > 216000) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} > + > +static bool > +ingenic_dw_hdmi_mode_fixup(struct drm_bridge *bridge, > + const struct drm_display_mode *mode, > + struct drm_display_mode *adjusted_mode) > +{ > + adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); > + adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); > + > + return true; > +} > + > +static const struct drm_bridge_timings ingenic_dw_hdmi_timings = { > + .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, > +}; These should go in the intermediate encoder bridge callbacks Paul introduces in his patch at [1]. With that patch 4 can be dropped. [1] https://lore.kernel.org/r/20210922205555.496871-7-paul@crapouillou.net Neil > + > +static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = { > + .mpll_cfg = ingenic_mpll_cfg, > + .cur_ctr = ingenic_cur_ctr, > + .phy_config = ingenic_phy_config, > + .mode_valid = ingenic_dw_hdmi_mode_valid, > + .mode_fixup = ingenic_dw_hdmi_mode_fixup, > + .timings = &ingenic_dw_hdmi_timings, > + .output_port = 1, > +}; > + > +static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = { > + { .compatible = "ingenic,jz4780-dw-hdmi" }, > + { /* Sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids); > + > +static int ingenic_dw_hdmi_probe(struct platform_device *pdev) > +{ > + struct dw_hdmi *hdmi; > + struct regulator *regulator; > + int ret; > + > + hdmi = dw_hdmi_probe(pdev, &ingenic_dw_hdmi_plat_data); > + if (IS_ERR(hdmi)) > + return PTR_ERR(hdmi); > + > + platform_set_drvdata(pdev, hdmi); > + > + regulator = devm_regulator_get_optional(&pdev->dev, "hdmi-5v"); > + > + if (IS_ERR(regulator)) { > + ret = PTR_ERR(regulator); > + > + DRM_DEV_ERROR(&pdev->dev, "failed to get hpd regulator: %s (%d)\n", > + "hdmi-5v", ret); > + return ret; > + } > + > + ret = regulator_enable(regulator); > + if (ret) { > + DRM_DEV_ERROR(&pdev->dev, "Failed to enable hpd regulator: %d\n", > + ret); > + return ret; > + } > + > + return 0; > +} > + > +static int ingenic_dw_hdmi_remove(struct platform_device *pdev) > +{ > + struct dw_hdmi *hdmi = platform_get_drvdata(pdev); > + > + dw_hdmi_remove(hdmi); > + > + return 0; > +} > + > +static struct platform_driver ingenic_dw_hdmi_driver = { > + .probe = ingenic_dw_hdmi_probe, > + .remove = ingenic_dw_hdmi_remove, > + .driver = { > + .name = "dw-hdmi-ingenic", > + .of_match_table = ingenic_dw_hdmi_dt_ids, > + }, > +}; > + > +struct platform_driver *ingenic_dw_hdmi_driver_ptr = &ingenic_dw_hdmi_driver; >
Hi Neil, > Am 28.09.2021 um 15:02 schrieb Neil Armstrong <narmstrong@baylibre.com>: > > On 27/09/2021 18:44, H. Nikolaus Schaller wrote: >> From: Paul Boddie <paul@boddie.org.uk> >> >> A specialisation of the generic Synopsys HDMI driver is employed for JZ4780 >> HDMI support. This requires a new driver, plus device tree and configuration >> modifications. >> >> Signed-off-by: Paul Boddie <paul@boddie.org.uk> >> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> >> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> >> --- >> drivers/gpu/drm/ingenic/Kconfig | 9 ++ >> drivers/gpu/drm/ingenic/Makefile | 1 + >> drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 142 ++++++++++++++++++++++ >> 3 files changed, 152 insertions(+) >> create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c >> >> diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig >> index 3b57f8be007c..4c7d311fbeff 100644 >> --- a/drivers/gpu/drm/ingenic/Kconfig >> +++ b/drivers/gpu/drm/ingenic/Kconfig >> @@ -25,4 +25,13 @@ config DRM_INGENIC_IPU >> >> The Image Processing Unit (IPU) will appear as a second primary plane. >> >> +config DRM_INGENIC_DW_HDMI >> + bool "Ingenic specific support for Synopsys DW HDMI" >> + depends on MACH_JZ4780 >> + select DRM_DW_HDMI >> + help >> + Choose this option to enable Synopsys DesignWare HDMI based driver. >> + If you want to enable HDMI on Ingenic JZ4780 based SoC, you should >> + select this option.. >> + >> endif >> diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile >> index d313326bdddb..3db9888a6c04 100644 >> --- a/drivers/gpu/drm/ingenic/Makefile >> +++ b/drivers/gpu/drm/ingenic/Makefile >> @@ -1,3 +1,4 @@ >> obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o >> ingenic-drm-y = ingenic-drm-drv.o >> ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o >> +ingenic-drm-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o >> diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c >> new file mode 100644 >> index 000000000000..dd9c94ae842e >> --- /dev/null >> +++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c >> @@ -0,0 +1,142 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. >> + * Copyright (C) 2019, 2020 Paul Boddie <paul@boddie.org.uk> >> + * >> + * Derived from dw_hdmi-imx.c with i.MX portions removed. >> + * Probe and remove operations derived from rcar_dw_hdmi.c. >> + */ >> + >> +#include <linux/module.h> >> +#include <linux/platform_device.h> >> +#include <linux/regmap.h> >> + >> +#include <drm/bridge/dw_hdmi.h> >> +#include <drm/drm_of.h> >> +#include <drm/drm_print.h> >> + >> +static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = { >> + { 45250000, { { 0x01e0, 0x0000 }, { 0x21e1, 0x0000 }, { 0x41e2, 0x0000 } } }, >> + { 92500000, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, 0x0005 } } }, >> + { 148500000, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, 0x000a } } }, >> + { 216000000, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f } } }, >> + { ~0UL, { { 0x0000, 0x0000 }, { 0x0000, 0x0000 }, { 0x0000, 0x0000 } } } >> +}; >> + >> +static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = { >> + /*pixelclk bpp8 bpp10 bpp12 */ >> + { 54000000, { 0x091c, 0x091c, 0x06dc } }, >> + { 58400000, { 0x091c, 0x06dc, 0x06dc } }, >> + { 72000000, { 0x06dc, 0x06dc, 0x091c } }, >> + { 74250000, { 0x06dc, 0x0b5c, 0x091c } }, >> + { 118800000, { 0x091c, 0x091c, 0x06dc } }, >> + { 216000000, { 0x06dc, 0x0b5c, 0x091c } }, >> + { ~0UL, { 0x0000, 0x0000, 0x0000 } }, >> +}; >> + >> +/* >> + * Resistance term 133Ohm Cfg >> + * PREEMP config 0.00 >> + * TX/CK level 10 >> + */ >> +static const struct dw_hdmi_phy_config ingenic_phy_config[] = { >> + /*pixelclk symbol term vlev */ >> + { 216000000, 0x800d, 0x0005, 0x01ad}, >> + { ~0UL, 0x0000, 0x0000, 0x0000} >> +}; >> + >> +static enum drm_mode_status >> +ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, >> + const struct drm_display_info *info, >> + const struct drm_display_mode *mode) >> +{ >> + if (mode->clock < 13500) >> + return MODE_CLOCK_LOW; >> + /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */ >> + if (mode->clock > 216000) >> + return MODE_CLOCK_HIGH; >> + >> + return MODE_OK; >> +} >> + >> +static bool >> +ingenic_dw_hdmi_mode_fixup(struct drm_bridge *bridge, >> + const struct drm_display_mode *mode, >> + struct drm_display_mode *adjusted_mode) >> +{ >> + adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); >> + adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); >> + >> + return true; >> +} >> + >> +static const struct drm_bridge_timings ingenic_dw_hdmi_timings = { >> + .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, >> +}; > > These should go in the intermediate encoder bridge callbacks Paul introduces in his patch at [1]. > > With that patch 4 can be dropped. > > [1] https://lore.kernel.org/r/20210922205555.496871-7-paul@crapouillou.net > > Neil Sorry, but I can't follow you here. Our patch set is on top of Paul's patch [1] and requires Paul's work to be merged first. And our 4/10 is needed to specialize dw-hdmi to the jz4780 like it is done for other SoC integration. It addresses a different stage of the jz4780 HDMI chain than [1]. BR, Nikolaus
Hi Nikolaus & Paul, Le lun., sept. 27 2021 at 18:44:24 +0200, H. Nikolaus Schaller <hns@goldelico.com> a écrit : > From: Paul Boddie <paul@boddie.org.uk> > > A specialisation of the generic Synopsys HDMI driver is employed for > JZ4780 > HDMI support. This requires a new driver, plus device tree and > configuration > modifications. > > Signed-off-by: Paul Boddie <paul@boddie.org.uk> > Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > drivers/gpu/drm/ingenic/Kconfig | 9 ++ > drivers/gpu/drm/ingenic/Makefile | 1 + > drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 142 > ++++++++++++++++++++++ > 3 files changed, 152 insertions(+) > create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c > > diff --git a/drivers/gpu/drm/ingenic/Kconfig > b/drivers/gpu/drm/ingenic/Kconfig > index 3b57f8be007c..4c7d311fbeff 100644 > --- a/drivers/gpu/drm/ingenic/Kconfig > +++ b/drivers/gpu/drm/ingenic/Kconfig > @@ -25,4 +25,13 @@ config DRM_INGENIC_IPU > > The Image Processing Unit (IPU) will appear as a second primary > plane. > > +config DRM_INGENIC_DW_HDMI > + bool "Ingenic specific support for Synopsys DW HDMI" > + depends on MACH_JZ4780 > + select DRM_DW_HDMI > + help > + Choose this option to enable Synopsys DesignWare HDMI based > driver. > + If you want to enable HDMI on Ingenic JZ4780 based SoC, you should > + select this option.. > + > endif > diff --git a/drivers/gpu/drm/ingenic/Makefile > b/drivers/gpu/drm/ingenic/Makefile > index d313326bdddb..3db9888a6c04 100644 > --- a/drivers/gpu/drm/ingenic/Makefile > +++ b/drivers/gpu/drm/ingenic/Makefile > @@ -1,3 +1,4 @@ > obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o > ingenic-drm-y = ingenic-drm-drv.o > ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o > +ingenic-drm-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o > diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c > b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c > new file mode 100644 > index 000000000000..dd9c94ae842e > --- /dev/null > +++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c > @@ -0,0 +1,142 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. > + * Copyright (C) 2019, 2020 Paul Boddie <paul@boddie.org.uk> > + * > + * Derived from dw_hdmi-imx.c with i.MX portions removed. > + * Probe and remove operations derived from rcar_dw_hdmi.c. > + */ > + > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > + > +#include <drm/bridge/dw_hdmi.h> > +#include <drm/drm_of.h> > +#include <drm/drm_print.h> > + > +static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = { > + { 45250000, { { 0x01e0, 0x0000 }, { 0x21e1, 0x0000 }, { 0x41e2, > 0x0000 } } }, > + { 92500000, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, > 0x0005 } } }, > + { 148500000, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, > 0x000a } } }, > + { 216000000, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, > 0x000f } } }, > + { ~0UL, { { 0x0000, 0x0000 }, { 0x0000, 0x0000 }, { 0x0000, > 0x0000 } } } > +}; > + > +static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = { > + /*pixelclk bpp8 bpp10 bpp12 */ > + { 54000000, { 0x091c, 0x091c, 0x06dc } }, > + { 58400000, { 0x091c, 0x06dc, 0x06dc } }, > + { 72000000, { 0x06dc, 0x06dc, 0x091c } }, > + { 74250000, { 0x06dc, 0x0b5c, 0x091c } }, > + { 118800000, { 0x091c, 0x091c, 0x06dc } }, > + { 216000000, { 0x06dc, 0x0b5c, 0x091c } }, > + { ~0UL, { 0x0000, 0x0000, 0x0000 } }, > +}; > + > +/* > + * Resistance term 133Ohm Cfg > + * PREEMP config 0.00 > + * TX/CK level 10 > + */ > +static const struct dw_hdmi_phy_config ingenic_phy_config[] = { > + /*pixelclk symbol term vlev */ > + { 216000000, 0x800d, 0x0005, 0x01ad}, > + { ~0UL, 0x0000, 0x0000, 0x0000} > +}; > + > +static enum drm_mode_status > +ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, > + const struct drm_display_info *info, > + const struct drm_display_mode *mode) > +{ > + if (mode->clock < 13500) > + return MODE_CLOCK_LOW; > + /* FIXME: Hardware is capable of 270MHz, but setup data is missing. > */ > + if (mode->clock > 216000) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} > + > +static bool > +ingenic_dw_hdmi_mode_fixup(struct drm_bridge *bridge, > + const struct drm_display_mode *mode, > + struct drm_display_mode *adjusted_mode) > +{ > + adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | > DRM_MODE_FLAG_PVSYNC); > + adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | > DRM_MODE_FLAG_NVSYNC); Why do these flags need to be cleared? The LCDC can work with negative v/h sync, does the HDMI core not work with that? > + > + return true; > +} > + > +static const struct drm_bridge_timings ingenic_dw_hdmi_timings = { > + .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, That info should be provided in the EDID, is this really needed here? Cheers, -Paul > +}; > + > +static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = { > + .mpll_cfg = ingenic_mpll_cfg, > + .cur_ctr = ingenic_cur_ctr, > + .phy_config = ingenic_phy_config, > + .mode_valid = ingenic_dw_hdmi_mode_valid, > + .mode_fixup = ingenic_dw_hdmi_mode_fixup, > + .timings = &ingenic_dw_hdmi_timings, > + .output_port = 1, > +}; > + > +static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = { > + { .compatible = "ingenic,jz4780-dw-hdmi" }, > + { /* Sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids); > + > +static int ingenic_dw_hdmi_probe(struct platform_device *pdev) > +{ > + struct dw_hdmi *hdmi; > + struct regulator *regulator; > + int ret; > + > + hdmi = dw_hdmi_probe(pdev, &ingenic_dw_hdmi_plat_data); > + if (IS_ERR(hdmi)) > + return PTR_ERR(hdmi); > + > + platform_set_drvdata(pdev, hdmi); > + > + regulator = devm_regulator_get_optional(&pdev->dev, "hdmi-5v"); > + > + if (IS_ERR(regulator)) { > + ret = PTR_ERR(regulator); > + > + DRM_DEV_ERROR(&pdev->dev, "failed to get hpd regulator: %s (%d)\n", > + "hdmi-5v", ret); > + return ret; > + } > + > + ret = regulator_enable(regulator); > + if (ret) { > + DRM_DEV_ERROR(&pdev->dev, "Failed to enable hpd regulator: %d\n", > + ret); > + return ret; > + } > + > + return 0; > +} > + > +static int ingenic_dw_hdmi_remove(struct platform_device *pdev) > +{ > + struct dw_hdmi *hdmi = platform_get_drvdata(pdev); > + > + dw_hdmi_remove(hdmi); > + > + return 0; > +} > + > +static struct platform_driver ingenic_dw_hdmi_driver = { > + .probe = ingenic_dw_hdmi_probe, > + .remove = ingenic_dw_hdmi_remove, > + .driver = { > + .name = "dw-hdmi-ingenic", > + .of_match_table = ingenic_dw_hdmi_dt_ids, > + }, > +}; > + > +struct platform_driver *ingenic_dw_hdmi_driver_ptr = > &ingenic_dw_hdmi_driver; > -- > 2.31.1 >
Hi Paul, > Am 28.09.2021 um 14:06 schrieb H. Nikolaus Schaller <hns@goldelico.com>: > > Hi Paul, > >> Am 28.09.2021 um 12:21 schrieb H. Nikolaus Schaller <hns@goldelico.com>: >> >>>> @@ -1492,10 +1555,16 @@ static int ingenic_drm_init(void) >>>> { >>>> int err; >>>> + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) { >>>> + err = platform_driver_register(ingenic_dw_hdmi_driver_ptr); >>>> + if (err) >>>> + return err; >>>> + } >>> >>> I don't see why you need to register the ingenic-dw-hdmi driver here. Just register it in the ingenic-dw-hdmi driver. >> >> Ok, I never though about this (as the code was not from me). We apparently just followed the IPU code pattern (learning by example). >> >> It indeed looks not necessary and would also avoid the ingenic_dw_hdmi_driver_ptr dependency. >> >> But: what is ingenic_ipu_driver_ptr then good for? >> >> If we can get rid of this as well, we can drop patch 1/10 ("drm/ingenic: Fix drm_init error path if IPU was registered") completely. > > A quick test shows that it *is* required. At least if I configure everything as modules. > But like you I can't explain why. > > Well, just a very rough idea (may be wrong): the bridge chain is not like an i2c bus and > clients are not automatically loaded/probed if linked in the device tree. Therefore the > consumer (ingenic_drm_drv) must register the "clients" like IPU and HDMI. Any suggestion how to proceed here for v5? BR, Nikolaus
Hi, Le mar., sept. 28 2021 at 14:06:03 +0200, H. Nikolaus Schaller <hns@goldelico.com> a écrit : > Hi Paul, > >> Am 28.09.2021 um 12:21 schrieb H. Nikolaus Schaller >> <hns@goldelico.com>: >> >>>> @@ -1492,10 +1555,16 @@ static int ingenic_drm_init(void) >>>> { >>>> int err; >>>> + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) { >>>> + err = platform_driver_register(ingenic_dw_hdmi_driver_ptr); >>>> + if (err) >>>> + return err; >>>> + } >>> >>> I don't see why you need to register the ingenic-dw-hdmi driver >>> here. Just register it in the ingenic-dw-hdmi driver. >> >> Ok, I never though about this (as the code was not from me). We >> apparently just followed the IPU code pattern (learning by example). >> >> It indeed looks not necessary and would also avoid the >> ingenic_dw_hdmi_driver_ptr dependency. >> >> But: what is ingenic_ipu_driver_ptr then good for? >> It's done this way because ingenic-drm-drv.c and ingenic-ipu.c are both compiled within the same module ingenic-drm. I'm not sure this is still required, maybe ingenic-ipu.c can be its own module now. >> >> If we can get rid of this as well, we can drop patch 1/10 >> ("drm/ingenic: Fix drm_init error path if IPU was registered") >> completely. > > A quick test shows that it *is* required. At least if I configure > everything as modules. > But like you I can't explain why. Well, a quick test here shows that it is not required, at least when configuring with everything built-in. -Paul > Well, just a very rough idea (may be wrong): the bridge chain is not > like an i2c bus and > clients are not automatically loaded/probed if linked in the device > tree. Therefore the > consumer (ingenic_drm_drv) must register the "clients" like IPU and > HDMI. > > BR, > Nikolaus >
Hi Paul, > Am 29.09.2021 um 16:30 schrieb Paul Cercueil <paul@crapouillou.net>: > > Hi, > > Le mar., sept. 28 2021 at 14:06:03 +0200, H. Nikolaus Schaller <hns@goldelico.com> a écrit : >> Hi Paul, >>> Am 28.09.2021 um 12:21 schrieb H. Nikolaus Schaller <hns@goldelico.com>: >>>>> @@ -1492,10 +1555,16 @@ static int ingenic_drm_init(void) >>>>> { >>>>> int err; >>>>> + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) { >>>>> + err = platform_driver_register(ingenic_dw_hdmi_driver_ptr); >>>>> + if (err) >>>>> + return err; >>>>> + } >>>> I don't see why you need to register the ingenic-dw-hdmi driver here. Just register it in the ingenic-dw-hdmi driver. >>> Ok, I never though about this (as the code was not from me). We apparently just followed the IPU code pattern (learning by example). >>> It indeed looks not necessary and would also avoid the ingenic_dw_hdmi_driver_ptr dependency. >>> But: what is ingenic_ipu_driver_ptr then good for? > > It's done this way because ingenic-drm-drv.c and ingenic-ipu.c are both compiled within the same module ingenic-drm. Ah, I see. Hadn't checked this. > I'm not sure this is still required, maybe ingenic-ipu.c can be its own module now. What I have seen is that it has its own compatible record. So there could be load-on-demand by DTS. > >>> If we can get rid of this as well, we can drop patch 1/10 ("drm/ingenic: Fix drm_init error path if IPU was registered") completely. >> A quick test shows that it *is* required. At least if I configure everything as modules. >> But like you I can't explain why. > > Well, a quick test here shows that it is not required, at least when configuring with everything built-in. IMHO the hdmi driver (module) should be loaded on demand. Not everyone wants to have it. Well, that is the problem that needs to be solved... BR and thanks, Nikolaus
- fix setting output_port = 1 (issue found by paul@crapouillou.net) - ci20.dts: convert to use hdmi-connector (by hns@goldelico.com) - add a hdmi-regulator to control +5V power (by hns@goldelico.com) - added a fix to dw-hdmi to call drm_kms_helper_hotplug_event on plugin event detection (by hns@goldelico.com) - always allocate extended descriptor but initialize only for jz4780 (by hns@goldelico.com) - updated to work on top of "[PATCH v3 0/6] drm/ingenic: Various improvements v3" (by paul@crapouillou.net) - rebased to v5.13-rc3 PATCH V3 2021-08-08 07:10:50: This series adds HDMI support for JZ4780 and CI20 board (and fixes one IPU related issue in registration error path) - [patch 1/8] switched from mode_fixup to atomic_check (suggested by robert.foss@linaro.org) - the call to the dw-hdmi specialization is still called mode_fixup - [patch 3/8] diverse fixes for ingenic-drm-drv (suggested by paul@crapouillou.net) - factor out some non-HDMI features of the jz4780 into a separate patch - multiple fixes around max height - do not change regmap config but a copy on stack - define some constants - factor out fixing of drm_init error path for IPU into separate patch - use FIELD_PREP() - [patch 8/8] conversion to component framework dropped (suggested by Laurent.pinchart@ideasonboard.com and paul@crapouillou.net) PATCH V2 2021-08-05 16:08:05: This series adds HDMI support for JZ4780 and CI20 board V2: - code and commit messages revisited for checkpatch warnings - rebased on v5.14-rc4 - include (failed, hence RFC 8/8) attempt to convert to component framework (was suggested by Paul Cercueil <paul@crapouillou.net> a while ago) H. Nikolaus Schaller (2): drm/bridge: synopsis: Fix to properly handle HPD MIPS: defconfig: CI20: configure for DRM_DW_HDMI_JZ4780 Paul Boddie (7): drm/ingenic: Fix drm_init error path if IPU was registered drm/ingenic: Add support for JZ4780 and HDMI output drm/bridge: synopsis: Add mode_fixup and bridge timings support drm/ingenic: Add dw-hdmi driver for jz4780 MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers MIPS: DTS: CI20: Add DT nodes for HDMI setup drm/ingenic: add some jz4780 specific features Sam Ravnborg (1): dt-bindings: display: Add ingenic,jz4780-dw-hdmi DT Schema .../bindings/display/ingenic-jz4780-hdmi.yaml | 85 +++++++++++ arch/mips/boot/dts/ingenic/ci20.dts | 67 +++++++++ arch/mips/boot/dts/ingenic/jz4780.dtsi | 45 ++++++ arch/mips/configs/ci20_defconfig | 6 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 9 ++ drivers/gpu/drm/ingenic/Kconfig | 9 ++ drivers/gpu/drm/ingenic/Makefile | 1 + drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 135 ++++++++++++++++- drivers/gpu/drm/ingenic/ingenic-drm.h | 42 ++++++ drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 142 ++++++++++++++++++ include/drm/bridge/dw_hdmi.h | 5 + 11 files changed, 540 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c