| Message ID | cover.1623239033.git.michal.simek@xilinx.com |
|---|---|
| Headers | show |
| Series | arm64: zynqmp: Extend board description | expand |
Hi Michal, Thank you for the patch. On Wed, Jun 09, 2021 at 01:44:57PM +0200, Michal Simek wrote: > This location is used by others DTs files that's why this move. I like alphabetical order :-) > Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > > .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 22 +++++++++---------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts > index dbb8bfbb5c7f..4a0f3370bf7f 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts > @@ -160,17 +160,6 @@ &dcc { > status = "okay"; > }; > > -&zynqmp_dpdma { > - status = "okay"; > -}; > - > -&zynqmp_dpsub { > - status = "okay"; > - phy-names = "dp-phy0", "dp-phy1"; > - phys = <&psgtr 1 PHY_TYPE_DP 0 3>, > - <&psgtr 0 PHY_TYPE_DP 1 3>; > -}; > - > /* fpd_dma clk 667MHz, lpd_dma 500MHz */ > &fpd_dma_chan1 { > status = "okay"; > @@ -994,3 +983,14 @@ &usb0 { > &watchdog0 { > status = "okay"; > }; > + > +&zynqmp_dpdma { > + status = "okay"; > +}; > + > +&zynqmp_dpsub { > + status = "okay"; > + phy-names = "dp-phy0", "dp-phy1"; > + phys = <&psgtr 1 PHY_TYPE_DP 0 3>, > + <&psgtr 0 PHY_TYPE_DP 1 3>; > +};
Hi Michal, On 6/9/21 7:45 PM, Michal Simek wrote: > Couple of boards have qspi on the board that's why enable controller and > describe them. > > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > .../arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 16 +++++++++++++++- > .../arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 16 +++++++++++++++- > .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 14 ++++++++++++++ > .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 14 ++++++++++++++ > .../arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 15 +++++++++++++++ > .../arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 14 ++++++++++++++ > .../arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++ > .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 15 +++++++++++++++ > .../arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 15 +++++++++++++++ > 9 files changed, 121 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts > index 2e05fa416955..f1598527e5ec 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts > @@ -2,7 +2,7 @@ > /* > * dts file for Xilinx ZynqMP ZC1232 > * > - * (C) Copyright 2017 - 2019, Xilinx, Inc. > + * (C) Copyright 2017 - 2021, Xilinx, Inc. > * > * Michal Simek <michal.simek@xilinx.com> > */ > @@ -19,6 +19,7 @@ / { > aliases { > serial0 = &uart0; > serial1 = &dcc; > + spi0 = &qspi; > }; > > chosen { > @@ -36,6 +37,19 @@ &dcc { > status = "okay"; > }; > > +&qspi { > + status = "okay"; > + flash@0 { > + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; > + spi-max-frequency = <108000000>; /* Based on DC1 spec */ > + }; > +}; > + > &sata { > status = "okay"; > /* SATA OOB timing settings */ > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts > index 3d0aaa02f184..04efa1683eaa 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts > @@ -2,7 +2,7 @@ > /* > * dts file for Xilinx ZynqMP ZC1254 > * > - * (C) Copyright 2015 - 2019, Xilinx, Inc. > + * (C) Copyright 2015 - 2021, Xilinx, Inc. > * > * Michal Simek <michal.simek@xilinx.com> > * Siva Durga Prasad Paladugu <sivadur@xilinx.com> > @@ -20,6 +20,7 @@ / { > aliases { > serial0 = &uart0; > serial1 = &dcc; > + spi0 = &qspi; > }; > > chosen { > @@ -37,6 +38,19 @@ &dcc { > status = "okay"; > }; > > +&qspi { > + status = "okay"; > + flash@0 { > + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ > + spi-max-frequency = <108000000>; /* Based on DC1 spec */ > + }; > +}; > + > &uart0 { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts > index cd406947ec34..9f176307b62a 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts > @@ -26,6 +26,7 @@ aliases { > mmc1 = &sdhci1; > rtc0 = &rtc; > serial0 = &uart0; > + spi0 = &qspi; > }; > > chosen { > @@ -339,6 +340,19 @@ conf { > }; > }; > > +&qspi { > + status = "okay"; > + flash@0 { > + compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; > + spi-max-frequency = <108000000>; /* Based on DC1 spec */ > + }; > +}; > + > &rtc { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts > index 8046f0df0f35..05a2b79738af 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts > @@ -26,6 +26,7 @@ aliases { > rtc0 = &rtc; > serial0 = &uart0; > serial1 = &uart1; > + spi0 = &qspi; > }; > > chosen { > @@ -161,6 +162,19 @@ &i2c1 { > status = "okay"; > }; > > +&qspi { > + status = "okay"; > + flash@0 { > + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; /* also DUAL configuration possible */ > + spi-max-frequency = <108000000>; /* Based on DC1 spec */ > + }; > +}; > + > &rtc { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts > index 3cbc51b4587d..becfc23a5610 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts > @@ -30,6 +30,7 @@ aliases { > serial0 = &uart0; > serial1 = &uart1; > serial2 = &dcc; > + spi0 = &qspi; > }; > > chosen { > @@ -934,6 +935,20 @@ &psgtr { > clock-names = "ref0", "ref1", "ref2", "ref3"; > }; > > +&qspi { > + status = "okay"; > + is-dual = <1>; > + flash@0 { > + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ Maybe here should be "64MB" not "32MB". There are 2 mt25qu512a flashes at zcu102 board, and each of them is 64MB. Since "is-dual" mode is not enabled, so we can only observe 64MB size from boot log: spi-nor spi0.0: found mt25qu512a, expected m25p80 spi-nor spi0.0: mt25qu512a (65536 Kbytes) And I only verify the flash size in zcu102 board and not sure if the flash size comments are correct for other boards in this patch. Thanks, Quanyang > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ > + spi-max-frequency = <108000000>; /* Based on DC1 spec */ > + }; > +}; > + > &rtc { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts > index 4c328569c3ac..84c4a9003e2e 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts > @@ -28,6 +28,7 @@ aliases { > serial0 = &uart0; > serial1 = &uart1; > serial2 = &dcc; > + spi0 = &qspi; > }; > > chosen { > @@ -427,6 +428,19 @@ &psgtr { > clock-names = "ref1", "ref2", "ref3"; > }; > > +&qspi { > + status = "okay"; > + flash@0 { > + compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; > + spi-max-frequency = <108000000>; /* Based on DC1 spec */ > + }; > +}; > + > &sata { > status = "okay"; > /* SATA OOB timing settings */ > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts > index 99d172867f6a..fb8d76b5c27f 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts > @@ -28,6 +28,7 @@ aliases { > serial0 = &uart0; > serial1 = &uart1; > serial2 = &dcc; > + spi0 = &qspi; > }; > > chosen { > @@ -435,6 +436,9 @@ flash@0 { > #address-cells = <1>; > #size-cells = <1>; > reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; > + spi-max-frequency = <108000000>; /* Based on DC1 spec */ > }; > }; > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts > index 464a76a13c24..d2219373580a 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts > @@ -30,6 +30,7 @@ aliases { > serial0 = &uart0; > serial1 = &uart1; > serial2 = &dcc; > + spi0 = &qspi; > }; > > chosen { > @@ -928,6 +929,20 @@ &psgtr { > clock-names = "ref1", "ref2", "ref3"; > }; > > +&qspi { > + status = "okay"; > + is-dual = <1>; > + flash@0 { > + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ > + spi-max-frequency = <108000000>; /* Based on DC1 spec */ > + }; > +}; > + > &rtc { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts > index c9d41d16c3f0..4dc315ee91b7 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts > @@ -29,6 +29,7 @@ aliases { > rtc0 = &rtc; > serial0 = &uart0; > serial1 = &dcc; > + spi0 = &qspi; > }; > > chosen { > @@ -772,6 +773,20 @@ &psgtr { > clock-names = "ref1", "ref2", "ref3"; > }; > > +&qspi { > + status = "okay"; > + is-dual = <1>; > + flash@0 { > + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ > + spi-max-frequency = <108000000>; /* Based on DC1 spec */ > + }; > +}; > + > &rtc { > status = "okay"; > }; >
Hi Michal, On 6/16/21 6:52 PM, Michal Simek wrote: > Hi Quanyang, > > On 6/10/21 6:08 AM, quanyang.wang wrote: >> Hi Michal, >> >> On 6/9/21 7:45 PM, Michal Simek wrote: >>> Couple of boards have qspi on the board that's why enable controller and >>> describe them. >>> >>> Signed-off-by: Michal Simek <michal.simek@xilinx.com> >>> --- >>> >>> .../arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 16 +++++++++++++++- >>> .../arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 16 +++++++++++++++- >>> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 14 ++++++++++++++ >>> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 14 ++++++++++++++ >>> .../arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 15 +++++++++++++++ >>> .../arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 14 ++++++++++++++ >>> .../arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++ >>> .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 15 +++++++++++++++ >>> .../arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 15 +++++++++++++++ >>> 9 files changed, 121 insertions(+), 2 deletions(-) >>> >>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts >>> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts >>> index 2e05fa416955..f1598527e5ec 100644 >>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts >>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts >>> @@ -2,7 +2,7 @@ >>> /* >>> * dts file for Xilinx ZynqMP ZC1232 >>> * >>> - * (C) Copyright 2017 - 2019, Xilinx, Inc. >>> + * (C) Copyright 2017 - 2021, Xilinx, Inc. >>> * >>> * Michal Simek <michal.simek@xilinx.com> >>> */ >>> @@ -19,6 +19,7 @@ / { >>> aliases { >>> serial0 = &uart0; >>> serial1 = &dcc; >>> + spi0 = &qspi; >>> }; >>> chosen { >>> @@ -36,6 +37,19 @@ &dcc { >>> status = "okay"; >>> }; >>> +&qspi { >>> + status = "okay"; >>> + flash@0 { >>> + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + reg = <0x0>; >>> + spi-tx-bus-width = <1>; >>> + spi-rx-bus-width = <4>; >>> + spi-max-frequency = <108000000>; /* Based on DC1 spec */ >>> + }; >>> +}; >>> + >>> &sata { >>> status = "okay"; >>> /* SATA OOB timing settings */ >>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts >>> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts >>> index 3d0aaa02f184..04efa1683eaa 100644 >>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts >>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts >>> @@ -2,7 +2,7 @@ >>> /* >>> * dts file for Xilinx ZynqMP ZC1254 >>> * >>> - * (C) Copyright 2015 - 2019, Xilinx, Inc. >>> + * (C) Copyright 2015 - 2021, Xilinx, Inc. >>> * >>> * Michal Simek <michal.simek@xilinx.com> >>> * Siva Durga Prasad Paladugu <sivadur@xilinx.com> >>> @@ -20,6 +20,7 @@ / { >>> aliases { >>> serial0 = &uart0; >>> serial1 = &dcc; >>> + spi0 = &qspi; >>> }; >>> chosen { >>> @@ -37,6 +38,19 @@ &dcc { >>> status = "okay"; >>> }; >>> +&qspi { >>> + status = "okay"; >>> + flash@0 { >>> + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + reg = <0x0>; >>> + spi-tx-bus-width = <1>; >>> + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration >>> possible */ >>> + spi-max-frequency = <108000000>; /* Based on DC1 spec */ >>> + }; >>> +}; >>> + >>> &uart0 { >>> status = "okay"; >>> }; >>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts >>> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts >>> index cd406947ec34..9f176307b62a 100644 >>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts >>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts >>> @@ -26,6 +26,7 @@ aliases { >>> mmc1 = &sdhci1; >>> rtc0 = &rtc; >>> serial0 = &uart0; >>> + spi0 = &qspi; >>> }; >>> chosen { >>> @@ -339,6 +340,19 @@ conf { >>> }; >>> }; >>> +&qspi { >>> + status = "okay"; >>> + flash@0 { >>> + compatible = "m25p80", "jedec,spi-nor"; /* Micron >>> MT25QU512ABB8ESF */ >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + reg = <0x0>; >>> + spi-tx-bus-width = <1>; >>> + spi-rx-bus-width = <4>; >>> + spi-max-frequency = <108000000>; /* Based on DC1 spec */ >>> + }; >>> +}; >>> + >>> &rtc { >>> status = "okay"; >>> }; >>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts >>> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts >>> index 8046f0df0f35..05a2b79738af 100644 >>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts >>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts >>> @@ -26,6 +26,7 @@ aliases { >>> rtc0 = &rtc; >>> serial0 = &uart0; >>> serial1 = &uart1; >>> + spi0 = &qspi; >>> }; >>> chosen { >>> @@ -161,6 +162,19 @@ &i2c1 { >>> status = "okay"; >>> }; >>> +&qspi { >>> + status = "okay"; >>> + flash@0 { >>> + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + reg = <0x0>; >>> + spi-tx-bus-width = <1>; >>> + spi-rx-bus-width = <4>; /* also DUAL configuration possible */ >>> + spi-max-frequency = <108000000>; /* Based on DC1 spec */ >>> + }; >>> +}; >>> + >>> &rtc { >>> status = "okay"; >>> }; >>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts >>> b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts >>> index 3cbc51b4587d..becfc23a5610 100644 >>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts >>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts >>> @@ -30,6 +30,7 @@ aliases { >>> serial0 = &uart0; >>> serial1 = &uart1; >>> serial2 = &dcc; >>> + spi0 = &qspi; >>> }; >>> chosen { >>> @@ -934,6 +935,20 @@ &psgtr { >>> clock-names = "ref0", "ref1", "ref2", "ref3"; >>> }; >>> +&qspi { >>> + status = "okay"; >>> + is-dual = <1>; >>> + flash@0 { >>> + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ >> Maybe here should be "64MB" not "32MB". >> There are 2 mt25qu512a flashes at zcu102 board, and each of them is >> 64MB. Since "is-dual" mode is not enabled, so we can only observe 64MB >> size from boot log: >> >> spi-nor spi0.0: found mt25qu512a, expected m25p80 >> spi-nor spi0.0: mt25qu512a (65536 Kbytes) >> >> And I only verify the flash size in zcu102 board and not sure if the >> flash size comments are correct for other boards in this patch. > > I have double checked revA and it really has 16MB+16MB configuration > where only one is visible. Sorry for the noise. I made a mistake checking it at the board zcu102 Rev1.1 not RevA. Best Regards, Quanyang > I will use only half of that listed size which is corresponding with > single configuration and also remove is-dual from 102/106/111. > > This change will be in v3 version because forget to include it in v2. > > Thanks, > Michal >
Hi, over years couple of drivers were upstream and it is time to sync it up. On the top of it also adding new Kria boards which are using new overlay infrastructure which check if that overlays can be applied to base DT file. Thanks, Michal Amit Kumar Mahapatra (1): arm64: zynqmp: Do not duplicate flash partition label property Michal Simek (27): arm64: zynqmp: Disable CCI by default arm64: zynqmp: Enable fpd_dma for zcu104 platforms arm64: zynqmp: Fix irps5401 device nodes arm64: zynqmp: Add pinctrl description for all boards arm64: zynqmp: Correct zcu111 psgtr description arm64: zynqmp: Wire psgtr for zc1751-xm015 arm64: zynqmp: Correct psgtr description for zcu100-revC arm64: zynqmp: Add phy description for usb3.0 arm64: zynqmp: Disable WP on zcu111 arm64: zynqmp: Add missing mio-bank properties to dc1 and dc5 arm64: zynqmp: Wire DP and DPDMA for dc1/dc4 arm64: zynqmp: Enable nand driver for dc2 and dc3 arm64: zynqmp: Remove additional newline arm64: zynqmp: Move clock node to zynqmp-clk-ccf.dtsi arm64: zynqmp: Add nvmem alises for eeproms arm64: zynqmp: List reset property for ethernet phy arm64: zynqmp: Remove can aliases from zc1751 arm64: zynqmp: Move DP nodes to the end of file on zcu106 arm64: zynqmp: Add note about UHS mode on some boards arm64: zynqmp: Remove information about dma clock on zcu106 arm64: zynqmp: Wire qspi on multiple boards arm64: zynqmp: Move rtc to different location on zcu104-revA arm64: zynqmp: Add reset description for sata arm64: zynqmp: Sync psgtr node location with zcu104-revA arm64: zynqmp: Remove description for 8T49N287 and si5382 chips arm64: zynqmp: Add support for zcu102-rev1.1 board arm64: zynqmp: Add support for Xilinx Kria SOM board Mounika Grace Akula (1): arm64: zynqmp: Add reset-on-timeout to all boards and modify default timeout value Srinivas Neeli (1): arm64: zynqmp: Update rtc calibration value Stefano Stabellini (1): arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi .../devicetree/bindings/arm/xilinx.yaml | 32 ++ arch/arm64/boot/dts/xilinx/Makefile | 12 + .../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 13 +- .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dts | 371 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dts | 351 +++++++++++++++++ .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 289 ++++++++++++++ .../boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 21 + .../boot/dts/xilinx/zynqmp-zc1232-revA.dts | 16 +- .../boot/dts/xilinx/zynqmp-zc1254-revA.dts | 16 +- .../dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 289 +++++++++++++- .../dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 335 +++++++++++++++- .../dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 9 +- .../dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 24 +- .../dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 330 +++++++++++++++- .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 254 +++++++++++- .../boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts | 15 + .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 315 ++++++++++++++- .../boot/dts/xilinx/zynqmp-zcu102-revB.dts | 3 +- .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 286 +++++++++++++- .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 244 +++++++++++- .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 335 +++++++++++++++- .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 269 ++++++++++++- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 29 +- 23 files changed, 3776 insertions(+), 82 deletions(-) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts