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[0/4] soc: sifive: ccache: Add StarFive JH7100 support

Message ID CAJM55Z_pdoGxRXbmBgJ5GbVWyeM1N6+LHihbNdT26Oo_qA5VYA@mail.gmail.com
Headers show
Series soc: sifive: ccache: Add StarFive JH7100 support | expand

Message

Emil Renner Berthing Oct. 25, 2023, 6:56 p.m. UTC 
This series adds support for the StarFive JH7100 SoC to the SiFive cache
controller driver. The JH7100 was a "development version" of the JH7110
used on the BeagleV Starlight and VisionFive V1 boards.  It has
non-coherent peripheral DMAs but was designed before the standard RISC-V
Zicbom extension, so it neeeds support in this driver for non-standard
cache management.

Emil Renner Berthing (4):
  dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
  soc: sifive: ccache: Add StarFive JH7100 support
  dt-bindings: cache: sifive,ccache0: Add sifive,cache-ops property
  soc: sifive: ccache: Support cache management operations

 .../bindings/cache/sifive,ccache0.yaml        | 11 +++-
 drivers/soc/sifive/sifive_ccache.c            | 56 ++++++++++++++++++-
 2 files changed, 64 insertions(+), 3 deletions(-)

Comments

Emil Renner Berthing Oct. 25, 2023, 7:06 p.m. UTC | #1 
Emil Renner Berthing wrote:
> This series adds support for the StarFive JH7100 SoC to the SiFive cache
> controller driver. The JH7100 was a "development version" of the JH7110
> used on the BeagleV Starlight and VisionFive V1 boards.  It has
> non-coherent peripheral DMAs but was designed before the standard RISC-V
> Zicbom extension, so it neeeds support in this driver for non-standard
> cache management.

Ugh, sorry about the broken threading and From vs. Signed-off-by's.
Will fix in v2.

/Emil