| Message ID | 20240416153805.431118-1-angelogioacchino.delregno@collabora.com |
|---|---|
| Headers | show |
| Series | MediaTek DVFSRC Bus Bandwidth and Regulator knobs | expand |
On Tue, Apr 16, 2024 at 05:38:04PM +0200, AngeloGioacchino Del Regno wrote: > This driver never worked, and never got even compiled, because it was > missing the DVFSRC driver entirely, including headers it relies on! > > Perform a full (or nearly full) refactoring of the MediaTek DVFSRC > controlled Regulators driver: this retains support for the MT6873, > MT8183 and MT8192 SoCs, and adds MT8195. > > As part of the refactoring, this driver is now probed using its own > devicetree compatible, as this is a child of the main DVFSRC driver > and gets probed as a subnode of that. Given what you're doing this would probably be easier to review as two commits, one removing the existing driver and another adding the new code.
Il 17/04/24 02:52, Mark Brown ha scritto: > On Tue, Apr 16, 2024 at 05:38:04PM +0200, AngeloGioacchino Del Regno wrote: >> This driver never worked, and never got even compiled, because it was >> missing the DVFSRC driver entirely, including headers it relies on! >> >> Perform a full (or nearly full) refactoring of the MediaTek DVFSRC >> controlled Regulators driver: this retains support for the MT6873, >> MT8183 and MT8192 SoCs, and adds MT8195. >> >> As part of the refactoring, this driver is now probed using its own >> devicetree compatible, as this is a child of the main DVFSRC driver >> and gets probed as a subnode of that. > > Given what you're doing this would probably be easier to review as > two commits, one removing the existing driver and another adding the new > code. Yeah, definitely.... I'll do that for v2. Cheers, Angelo
This series adds support for the MediaTek Dynamic Voltage and Frequency Scaling Resource Controller (DVFSRC), found on many MediaTek SoCs. This hardware collects requests from both software and the various remote processors embededd into the SoC, and decides about a minimum operating voltage and a minimum DRAM frequency to fulfill those requests, in an effort to provide the best achievable performance per watt. Such hardware IP is capable of transparently performing direct register R/W on all of the DVFSRC-controlled regulators and SoC bandwidth knobs. Summarizing how the DVFSRC works for Interconnect: ICC provider ICC Nodes ---- ---- _________ |CPU | |--- |VPU | _____ | |----- ---- | ---- | |->| DRAM | ---- | ---- |DRAM |->|scheduler|----- |GPU | |--- |DISP| | |->| (EMI) | ---- | ---- |_____|->|_________|---. ----- | ---- /|\ `-|MMSYS|--|--- |VDEC| | ----- | ---- | | ---- | change DRAM freq |--- |VENC| -------- | ---- SMC --> | DVFSRC | | ---- -------- |--- |IMG | | ---- | ---- |--- |CAM | ---- ...and for regulators, it's simply... SMC -> DVFSRC -> Regulator voltage decider -> (vreg) Registers R/W Please note that this series is based on an old (abandoned) series from MediaTek [1], and reuses some parts of the code found in that. Besides, included in this series, there's also a refactoring of the mtk-dvfsrc-regulator driver, which never got compiled at all, and would not build anyway because of missing headers and typos: that commit did not get any Fixes tag because, well, backporting makes no sense at all as the DVFSRC support - which is critical for that driver to work - is introduced with *this series*! :-) P.S.: The DVFSRC regulator is a requirement for the MediaTek UFSHCI controller's crypto boost feature, which is already upstream but lacking the actual regulator to work....... :-) [1]: https://lore.kernel.org/all/20210812085846.2628-1-dawei.chien@mediatek.com/ Cheers! AngeloGioacchino Del Regno (6): dt-bindings: soc: mediatek: Add DVFSRC bindings for MT8183 and MT8195 dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings dt-bindings: regulator: Add bindings for MediaTek DVFSRC Regulators soc: mediatek: Add MediaTek DVFS Resource Collector (DVFSRC) driver regulator: mtk-dvfsrc-regulator: Refactor and add MT8192/MT8195 vregs interconnect: mediatek: Add MediaTek MT8183/8195 EMI Interconnect driver .../interconnect/mediatek,mt8183-emi.yaml | 76 +++ .../mediatek,mt6873-dvfsrc-regulator.yaml | 71 +++ .../soc/mediatek/mediatek,mt8183-dvfsrc.yaml | 57 ++ drivers/interconnect/Kconfig | 1 + drivers/interconnect/Makefile | 1 + drivers/interconnect/mediatek/Kconfig | 32 + drivers/interconnect/mediatek/Makefile | 5 + drivers/interconnect/mediatek/icc-emi.c | 153 +++++ drivers/interconnect/mediatek/icc-emi.h | 40 ++ drivers/interconnect/mediatek/mt8183.c | 143 +++++ drivers/interconnect/mediatek/mt8195.c | 339 +++++++++++ drivers/regulator/mtk-dvfsrc-regulator.c | 242 ++++---- drivers/soc/mediatek/Kconfig | 11 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-dvfsrc.c | 551 ++++++++++++++++++ .../interconnect/mediatek,mt8183.h | 23 + .../interconnect/mediatek,mt8195.h | 44 ++ include/linux/soc/mediatek/dvfsrc.h | 36 ++ include/linux/soc/mediatek/mtk_sip_svc.h | 3 + 19 files changed, 1699 insertions(+), 130 deletions(-) create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml create mode 100644 drivers/interconnect/mediatek/Kconfig create mode 100644 drivers/interconnect/mediatek/Makefile create mode 100644 drivers/interconnect/mediatek/icc-emi.c create mode 100644 drivers/interconnect/mediatek/icc-emi.h create mode 100644 drivers/interconnect/mediatek/mt8183.c create mode 100644 drivers/interconnect/mediatek/mt8195.c create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c create mode 100644 include/dt-bindings/interconnect/mediatek,mt8183.h create mode 100644 include/dt-bindings/interconnect/mediatek,mt8195.h create mode 100644 include/linux/soc/mediatek/dvfsrc.h