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[v11,00/14] PCI: imx6: Clean up and add imx95 pci support

Message ID 20240220161924.3871774-1-Frank.Li@nxp.com
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Series PCI: imx6: Clean up and add imx95 pci support | expand

Message

Frank Li Feb. 20, 2024, 4:19 p.m. UTC 
first 6 patches use drvdata: flags to simplify some switch-case code.
Improve maintaince and easy to read code.

Then add imx95 basic pci host function.

follow two patch do endpoint code clean up.
Then add imx95 basic endpont function.

Compared with v2, added EP function support and some fixes,  please change
notes at each patches.

Change from v10 to v11
- Rebase to linux-pci/endpoint

Change from v9 to v10
- remove two patches:
>   dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ
>   PCI: imx6: Using "linux,pci-domain" as slot ID
it is not good solution to fixed hardcode check to get controller id.
Will see better solution later.

dt-binding pass pcie node:

pcie0: pcie@4c300000 {
                        compatible = "fsl,imx95-pcie";
                        reg = <0 0x4c300000 0 0x40000>,
                                <0 0x4c360000 0 0x10000>,
                                <0 0x4c340000 0 0x20000>,
                                <0 0x60100000 0 0xfe00000>;
                        reg-names = "dbi", "atu", "app", "config";
                        #address-cells = <3>;
                        #size-cells = <2>;
                        device_type = "pci";
                        linux,pci-domain = <0>;
                        bus-range = <0x00 0xff>;
                        ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
                                 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
                        num-lanes = <1>;
                        num-viewport = <8>;
                        interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "msi";
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0x7>;
                        interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
                                        <0 0 0 2 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
                                        <0 0 0 3 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
                                        <0 0 0 4 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
                        fsl,max-link-speed = <3>;
                        clocks = <&scmi_clk IMX95_CLK_HSIO>,
                                 <&scmi_clk IMX95_CLK_HSIOPLL>,
                                 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
                                 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
                        clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
                        assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
                                         <&scmi_clk IMX95_CLK_HSIOPLL>,
                                         <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
                        assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
                        assigned-clock-parents = <0>, <0>,
                                                 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
                        power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
                        /* 0x30~0x37 stream id for pci0 */
                        /*
                         * iommu-map = <0x000 &apps_smmu 0x30 0x1>,
                         * <0x100 &apps_smmu 0x31 0x1>;
                         */
                        status = "disabled";
                };

pcie1: pcie-ep@4c380000 {
                        compatible = "fsl,imx95-pcie-ep";
                        reg = <0 0x4c380000 0 0x20000>,
                              <0 0x4c3e0000 0 0x1000>,
                              <0 0x4c3a0000 0 0x1000>,
                              <0 0x4c3c0000 0 0x10000>,
                              <0 0x4c3f0000 0 0x10000>,
                              <0xa 0 1 0>;
                        reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
                        interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "dma";
                        fsl,max-link-speed = <3>;
                        clocks = <&scmi_clk IMX95_CLK_HSIO>,
                                 <&scmi_clk IMX95_CLK_HSIOPLL>,
                                 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
                                 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
                        clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
                        assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
                                         <&scmi_clk IMX95_CLK_HSIOPLL>,
                                         <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
                        assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
                        assigned-clock-parents = <0>, <0>,
                                                 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
                        power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
                        status = "disabled";
                };

Frank Li (13):
  PCI: imx6: Simplify clock handling by using clk_bulk*() function
  PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV
  PCI: imx6: Simplify reset handling by using by using
    *_FLAG_HAS_*_RESET
  PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask
  PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
  PCI: imx6: Simplify switch-case logic by involve init_phy callback
  dt-bindings: imx6q-pcie: Clean up irrationality clocks check
  dt-bindings: imx6q-pcie: Restruct reg and reg-name
  PCI: imx6: Add iMX95 PCIe Root Complex support
  PCI: imx6: Clean up get addr_space code
  PCI: imx6: Add epc_features in imx6_pcie_drvdata
  dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
  PCI: imx6: Add iMX95 Endpoint (EP) support

Richard Zhu (1):
  dt-bindings: imx6q-pcie: Add imx95 pcie compatible string

 .../bindings/pci/fsl,imx6q-pcie-common.yaml   |  17 +-
 .../bindings/pci/fsl,imx6q-pcie-ep.yaml       |  46 +-
 .../bindings/pci/fsl,imx6q-pcie.yaml          |  49 +-
 drivers/pci/controller/dwc/pci-imx6.c         | 634 ++++++++++--------
 4 files changed, 436 insertions(+), 310 deletions(-)

Comments

Lorenzo Pieralisi Feb. 21, 2024, 10:42 a.m. UTC | #1 
On Tue, Feb 20, 2024 at 11:19:20AM -0500, Frank Li wrote:
> Add iMX95 PCIe Root Complex support.
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> 
> Notes:
>     Change from v8 to v9
>     - Add mani's review tag
>     
>     Change from v7 to v8
>     - Update commit subject
>     - add const from regmap
>     - remove unnessary logic in imx6_pcie_deassert_core_reset()
>     
>     Change from v4 to v7
>     - none
>     Change from v1 to v3
>     - none
> 
>  drivers/pci/controller/dwc/pci-imx6.c | 82 +++++++++++++++++++++++++--
>  1 file changed, 77 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 71ce6b7ac1de0..582ba00d628a1 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -42,6 +42,25 @@
>  #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE	GENMASK(11, 8)
>  #define IMX8MQ_PCIE2_BASE_ADDR			0x33c00000
>  
> +#define IMX95_PCIE_PHY_GEN_CTRL			0x0
> +#define IMX95_PCIE_REF_USE_PAD			BIT(17)
> +
> +#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
> +#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)

These two defines are unused, I will remove them.

> +#define IMX95_PCIE_SS_RW_REG_0			0xf0
> +#define IMX95_PCIE_REF_CLKEN			BIT(23)
> +#define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
> +
> +#define IMX95_PE0_GEN_CTRL_1			0x1050
> +#define IMX95_PCIE_DEVICE_TYPE			GENMASK(3, 0)
> +
> +#define IMX95_PE0_GEN_CTRL_3			0x1058
> +#define IMX95_PCIE_LTSSM_EN			BIT(0)
> +
> +#define IMX95_PE0_PM_STS			0x1064
> +#define IMX95_PCIE_PM_LINKST_IN_L2		BIT(14)

These two defines are unused. I will remove them.

> +
>  #define to_imx6_pcie(x)	dev_get_drvdata((x)->dev)
>  
>  enum imx6_pcie_variants {
> @@ -52,6 +71,7 @@ enum imx6_pcie_variants {
>  	IMX8MQ,
>  	IMX8MM,
>  	IMX8MP,
> +	IMX95,
>  	IMX8MQ_EP,
>  	IMX8MM_EP,
>  	IMX8MP_EP,
> @@ -63,6 +83,7 @@ enum imx6_pcie_variants {
>  #define IMX6_PCIE_FLAG_HAS_PHYDRV			BIT(3)
>  #define IMX6_PCIE_FLAG_HAS_APP_RESET		BIT(4)
>  #define IMX6_PCIE_FLAG_HAS_PHY_RESET		BIT(5)
> +#define IMX6_PCIE_FLAG_HAS_SERDES		BIT(6)
>  
>  #define imx6_check_flag(pci, val)     (pci->drvdata->flags & val)
>  
> @@ -179,6 +200,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
>  	return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
>  }
>  
> +static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> +{
> +	regmap_update_bits(imx6_pcie->iomuxc_gpr,
> +			IMX95_PCIE_SS_RW_REG_0,
> +			IMX95_PCIE_PHY_CR_PARA_SEL,
> +			IMX95_PCIE_PHY_CR_PARA_SEL);
> +
> +	regmap_update_bits(imx6_pcie->iomuxc_gpr,
> +			   IMX95_PCIE_PHY_GEN_CTRL,
> +			   IMX95_PCIE_REF_USE_PAD, 0);
> +	regmap_update_bits(imx6_pcie->iomuxc_gpr,
> +			   IMX95_PCIE_SS_RW_REG_0,
> +			   IMX95_PCIE_REF_CLKEN,
> +			   IMX95_PCIE_REF_CLKEN);
> +
> +	return 0;
> +}
> +
>  static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
>  {
>  	const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
> @@ -575,6 +614,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
>  				   IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
>  		break;
>  	case IMX7D:
> +	case IMX95:
>  		break;
>  	case IMX8MM:
>  	case IMX8MM_EP:
> @@ -1279,12 +1319,32 @@ static int imx6_pcie_probe(struct platform_device *pdev)
>  		return PTR_ERR(imx6_pcie->turnoff_reset);
>  	}
>  
> +	if (imx6_pcie->drvdata->gpr) {
>  	/* Grab GPR config register range */
> -	imx6_pcie->iomuxc_gpr =
> -		 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
> -	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
> -		dev_err(dev, "unable to find iomuxc registers\n");
> -		return PTR_ERR(imx6_pcie->iomuxc_gpr);
> +		imx6_pcie->iomuxc_gpr =
> +			 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
> +		if (IS_ERR(imx6_pcie->iomuxc_gpr))
> +			return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
> +					     "unable to find iomuxc registers\n");
> +	}
> +
> +	if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) {
> +		void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app");
> +
> +		if (IS_ERR(off))
> +			return dev_err_probe(dev, PTR_ERR(off),
> +					     "unable to find serdes registers\n");
> +
> +		static const struct regmap_config regmap_config = {
> +			.reg_bits = 32,
> +			.val_bits = 32,
> +			.reg_stride = 4,
> +		};
> +
> +		imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, &regmap_config);
> +		if (IS_ERR(imx6_pcie->iomuxc_gpr))
> +			return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
> +					     "unable to find iomuxc registers\n");
>  	}
>  
>  	/* Grab PCIe PHY Tx Settings */
> @@ -1457,6 +1517,17 @@ static const struct imx6_pcie_drvdata drvdata[] = {
>  		.mode_off[0] = IOMUXC_GPR12,
>  		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
>  	},
> +	[IMX95] = {
> +		.variant = IMX95,
> +		.flags = IMX6_PCIE_FLAG_HAS_SERDES,
> +		.clk_names = imx8mq_clks,
> +		.clks_cnt = ARRAY_SIZE(imx8mq_clks),
> +		.ltssm_off = IMX95_PE0_GEN_CTRL_3,
> +		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
> +		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> +		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> +		.init_phy = imx95_pcie_init_phy,
> +	},
>  	[IMX8MQ_EP] = {
>  		.variant = IMX8MQ_EP,
>  		.flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
> @@ -1501,6 +1572,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
>  	{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
>  	{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
>  	{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
> +	{ .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
>  	{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
>  	{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
>  	{ .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
> -- 
> 2.34.1
>
Frank Li Feb. 21, 2024, 3:36 p.m. UTC | #2 
On Wed, Feb 21, 2024 at 11:42:41AM +0100, Lorenzo Pieralisi wrote:
> On Tue, Feb 20, 2024 at 11:19:20AM -0500, Frank Li wrote:
> > Add iMX95 PCIe Root Complex support.
> > 
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > 
> > Notes:
> >     Change from v8 to v9
> >     - Add mani's review tag
> >     
> >     Change from v7 to v8
> >     - Update commit subject
> >     - add const from regmap
> >     - remove unnessary logic in imx6_pcie_deassert_core_reset()
> >     
> >     Change from v4 to v7
> >     - none
> >     Change from v1 to v3
> >     - none
> > 
> >  drivers/pci/controller/dwc/pci-imx6.c | 82 +++++++++++++++++++++++++--
> >  1 file changed, 77 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index 71ce6b7ac1de0..582ba00d628a1 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -42,6 +42,25 @@
> >  #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE	GENMASK(11, 8)
> >  #define IMX8MQ_PCIE2_BASE_ADDR			0x33c00000
> >  
> > +#define IMX95_PCIE_PHY_GEN_CTRL			0x0
> > +#define IMX95_PCIE_REF_USE_PAD			BIT(17)
> > +
> > +#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
> > +#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)
> 
> These two defines are unused, I will remove them.
> 
> > +#define IMX95_PCIE_SS_RW_REG_0			0xf0
> > +#define IMX95_PCIE_REF_CLKEN			BIT(23)
> > +#define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
> > +
> > +#define IMX95_PE0_GEN_CTRL_1			0x1050
> > +#define IMX95_PCIE_DEVICE_TYPE			GENMASK(3, 0)
> > +
> > +#define IMX95_PE0_GEN_CTRL_3			0x1058
> > +#define IMX95_PCIE_LTSSM_EN			BIT(0)
> > +
> > +#define IMX95_PE0_PM_STS			0x1064
> > +#define IMX95_PCIE_PM_LINKST_IN_L2		BIT(14)
> 
> These two defines are unused. I will remove them.

Thanks.
let me know if need me send out revised patches.

Frank

> 
> > +
> >  #define to_imx6_pcie(x)	dev_get_drvdata((x)->dev)
> >  
> >  enum imx6_pcie_variants {
> > @@ -52,6 +71,7 @@ enum imx6_pcie_variants {
> >  	IMX8MQ,
> >  	IMX8MM,
> >  	IMX8MP,
> > +	IMX95,
> >  	IMX8MQ_EP,
> >  	IMX8MM_EP,
> >  	IMX8MP_EP,
> > @@ -63,6 +83,7 @@ enum imx6_pcie_variants {
> >  #define IMX6_PCIE_FLAG_HAS_PHYDRV			BIT(3)
> >  #define IMX6_PCIE_FLAG_HAS_APP_RESET		BIT(4)
> >  #define IMX6_PCIE_FLAG_HAS_PHY_RESET		BIT(5)
> > +#define IMX6_PCIE_FLAG_HAS_SERDES		BIT(6)
> >  
> >  #define imx6_check_flag(pci, val)     (pci->drvdata->flags & val)
> >  
> > @@ -179,6 +200,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
> >  	return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
> >  }
> >  
> > +static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> > +{
> > +	regmap_update_bits(imx6_pcie->iomuxc_gpr,
> > +			IMX95_PCIE_SS_RW_REG_0,
> > +			IMX95_PCIE_PHY_CR_PARA_SEL,
> > +			IMX95_PCIE_PHY_CR_PARA_SEL);
> > +
> > +	regmap_update_bits(imx6_pcie->iomuxc_gpr,
> > +			   IMX95_PCIE_PHY_GEN_CTRL,
> > +			   IMX95_PCIE_REF_USE_PAD, 0);
> > +	regmap_update_bits(imx6_pcie->iomuxc_gpr,
> > +			   IMX95_PCIE_SS_RW_REG_0,
> > +			   IMX95_PCIE_REF_CLKEN,
> > +			   IMX95_PCIE_REF_CLKEN);
> > +
> > +	return 0;
> > +}
> > +
> >  static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
> >  {
> >  	const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
> > @@ -575,6 +614,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
> >  				   IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
> >  		break;
> >  	case IMX7D:
> > +	case IMX95:
> >  		break;
> >  	case IMX8MM:
> >  	case IMX8MM_EP:
> > @@ -1279,12 +1319,32 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> >  		return PTR_ERR(imx6_pcie->turnoff_reset);
> >  	}
> >  
> > +	if (imx6_pcie->drvdata->gpr) {
> >  	/* Grab GPR config register range */
> > -	imx6_pcie->iomuxc_gpr =
> > -		 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
> > -	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
> > -		dev_err(dev, "unable to find iomuxc registers\n");
> > -		return PTR_ERR(imx6_pcie->iomuxc_gpr);
> > +		imx6_pcie->iomuxc_gpr =
> > +			 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
> > +		if (IS_ERR(imx6_pcie->iomuxc_gpr))
> > +			return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
> > +					     "unable to find iomuxc registers\n");
> > +	}
> > +
> > +	if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) {
> > +		void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app");
> > +
> > +		if (IS_ERR(off))
> > +			return dev_err_probe(dev, PTR_ERR(off),
> > +					     "unable to find serdes registers\n");
> > +
> > +		static const struct regmap_config regmap_config = {
> > +			.reg_bits = 32,
> > +			.val_bits = 32,
> > +			.reg_stride = 4,
> > +		};
> > +
> > +		imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, &regmap_config);
> > +		if (IS_ERR(imx6_pcie->iomuxc_gpr))
> > +			return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
> > +					     "unable to find iomuxc registers\n");
> >  	}
> >  
> >  	/* Grab PCIe PHY Tx Settings */
> > @@ -1457,6 +1517,17 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> >  		.mode_off[0] = IOMUXC_GPR12,
> >  		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> >  	},
> > +	[IMX95] = {
> > +		.variant = IMX95,
> > +		.flags = IMX6_PCIE_FLAG_HAS_SERDES,
> > +		.clk_names = imx8mq_clks,
> > +		.clks_cnt = ARRAY_SIZE(imx8mq_clks),
> > +		.ltssm_off = IMX95_PE0_GEN_CTRL_3,
> > +		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
> > +		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
> > +		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> > +		.init_phy = imx95_pcie_init_phy,
> > +	},
> >  	[IMX8MQ_EP] = {
> >  		.variant = IMX8MQ_EP,
> >  		.flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
> > @@ -1501,6 +1572,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
> >  	{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
> >  	{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
> >  	{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
> > +	{ .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
> >  	{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
> >  	{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
> >  	{ .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
> > -- 
> > 2.34.1
> >
Lorenzo Pieralisi Feb. 23, 2024, 3:23 p.m. UTC | #3 
On Tue, 20 Feb 2024 11:19:10 -0500, Frank Li wrote:
> first 6 patches use drvdata: flags to simplify some switch-case code.
> Improve maintaince and easy to read code.
> 
> Then add imx95 basic pci host function.
> 
> follow two patch do endpoint code clean up.
> Then add imx95 basic endpont function.
> 
> [...]

Applied to enumeration, thanks!

[01/14] PCI: imx6: Simplify clock handling by using clk_bulk*() function
        https://git.kernel.org/pci/pci/c/6a4018583875
[02/14] PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV
        https://git.kernel.org/pci/pci/c/4e37c2f48712
[03/14] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET
        https://git.kernel.org/pci/pci/c/666a7beb942c
[04/14] PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask
        https://git.kernel.org/pci/pci/c/cb7b0cd26d3a
[05/14] PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
        https://git.kernel.org/pci/pci/c/e35c3c580740
[06/14] PCI: imx6: Simplify switch-case logic by involve init_phy callback
        https://git.kernel.org/pci/pci/c/a6afefd72856
[07/14] dt-bindings: imx6q-pcie: Clean up irrationality clocks check
        https://git.kernel.org/pci/pci/c/0aa0c28fd259
[08/14] dt-bindings: imx6q-pcie: Restruct reg and reg-name
        https://git.kernel.org/pci/pci/c/0efd53a842c8
[09/14] dt-bindings: imx6q-pcie: Add imx95 pcie compatible string
        https://git.kernel.org/pci/pci/c/41b116c2cf24
[10/14] PCI: imx6: Add iMX95 PCIe Root Complex support
        https://git.kernel.org/pci/pci/c/98e97fb574b1
[11/14] PCI: imx6: Clean up get addr_space code
        https://git.kernel.org/pci/pci/c/b16b852e3175
[12/14] PCI: imx6: Add epc_features in imx6_pcie_drvdata
        https://git.kernel.org/pci/pci/c/e2f2029ddf3f
[13/14] dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
        https://git.kernel.org/pci/pci/c/4d80ef68c2c7
[14/14] PCI: imx6: Add iMX95 Endpoint (EP) support
        https://git.kernel.org/pci/pci/c/b73259dcd670

Thanks,
Lorenzo
Lorenzo Pieralisi Feb. 23, 2024, 3:30 p.m. UTC | #4 
On Fri, Feb 23, 2024 at 04:23:24PM +0100, Lorenzo Pieralisi wrote:
> On Tue, 20 Feb 2024 11:19:10 -0500, Frank Li wrote:
> > first 6 patches use drvdata: flags to simplify some switch-case code.
> > Improve maintaince and easy to read code.
> > 
> > Then add imx95 basic pci host function.
> > 
> > follow two patch do endpoint code clean up.
> > Then add imx95 basic endpont function.
> > 
> > [...]
> 
> Applied to enumeration, thanks!

Sorry, scripting messed it up, it is the controller/imx branch.

Thanks,
Lorenzo