| Message ID | 20240212-phy-hdptx-v3-0-2cde680cd024@collabora.com |
|---|---|
| Headers | show |
| Series | Add support for RK3588 HDMI/eDP Combo PHY | expand |
On 2/12/24 19:52, Cristian Ciocaltea wrote: > Add driver for the HDMI/eDP TX Combo PHY found on Rockchip RK3588 SoC. > > The PHY is based on a Samsung IP block and supports HDMI 2.1 TMDS, FRL > and eDP links. The maximum data rate is 12Gbps (FRL), while the minimum > is 250Mbps (TMDS). > > Only the TMDS link is currently supported. > > Co-developed-by: Algea Cao <algea.cao@rock-chips.com> > Signed-off-by: Algea Cao <algea.cao@rock-chips.com> > Tested-by: Heiko Stuebner <heiko@sntech.de> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> > --- For Linux FTRACE filters it is needed that all functions in a driver start with the same function prefix. Currently there's a mix of hdtpx_* and rockchip_* Maybe use rk_hdtpx_* ??? similar to for example rk_nfc_* in rockchip-nand-controller.c Johan
On 2/13/24 01:29, Johan Jonker wrote: > > On 2/12/24 19:52, Cristian Ciocaltea wrote: >> Add driver for the HDMI/eDP TX Combo PHY found on Rockchip RK3588 SoC. [...] > For Linux FTRACE filters it is needed that all functions in a driver start with the same function prefix. > Currently there's a mix of hdtpx_* and rockchip_* > Maybe use rk_hdtpx_* ??? similar to for example rk_nfc_* in rockchip-nand-controller.c Done in v4: https://lore.kernel.org/all/20240214-phy-hdptx-v4-0-e7974f46c1a7@collabora.com/ Thanks, Cristian
Add driver and bindings to add initial support the Rockchip HDMI/eDP TX Combo PHY found on RK3588 SoC. The PHY is based on a Samsung IP block and supports HDMI 2.1 TMDS, FRL and eDP links. Please note that currently only the TMDS related functionality has been implemented. This has been tested on Radxa ROCK 5B and Rockchip EVB1 boards. Changes in v3: - Collected R-b & T-b tags from Heiko - Converted all *_REG() args to lowercase (Vinod) - Dropped unnecessary register read/write wrappers (Vinod) - Added rate overflow check in hdptx_phy_clk_pll_calc() (Luis) - Link to v2: https://lore.kernel.org/r/20240205-phy-hdptx-v2-0-a7150814c047@collabora.com Changes in v2: - Rebased series onto next-20240129 - Removed patch 'dt-bindings: soc: rockchip: Add rk3588 hdptxphy syscon' already applied by Heiko - For consistency with SoC TRM, replaced all references to DP with eDP - Updated PHY schema per Krzysztof's review; also collected his R-b tag - Dropped FRL, EARC and 10-bit color depth functionality until the HDMI configuration options become available in PHY API - Squashed lots of regmap_write operations via regmap_multi_reg_write (Sebastian) - Introduced parametrized {CMN|SB|LNTOP|LANE}_REG() macros to replace the long list of register defines - Optimized handling of the config arrays by using ARRAY_SIZE() (Sascha) - Link to v1: https://lore.kernel.org/r/20240119193806.1030214-1-cristian.ciocaltea@collabora.com --- Cristian Ciocaltea (2): dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver .../bindings/phy/rockchip,rk3588-hdptx-phy.yaml | 91 ++ drivers/phy/rockchip/Kconfig | 8 + drivers/phy/rockchip/Makefile | 1 + drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 1028 ++++++++++++++++++++ 4 files changed, 1128 insertions(+) --- base-commit: 596764183be8ebb13352b281a442a1f1151c9b06 change-id: 20240128-phy-hdptx-8a98ab60d18e