mbox series

[v7,00/14] Add support for the Mobileye EyeQ5 SoC

Message ID 20240205153503.574468-1-gregory.clement@bootlin.com
Headers show
Series Add support for the Mobileye EyeQ5 SoC | expand

Message

Gregory CLEMENT Feb. 5, 2024, 3:34 p.m. UTC 
Hello,

The EyeQ5 SoC from Mobileye is based on the MIPS I6500 architecture
and features multiple controllers such as the classic UART, I2C, SPI,
as well as CAN-FD, PCIe, Octal/Quad SPI Flash interface, Gigabit
Ethernet, MIPI CSI-2, and eMMC 5.1. It also includes a Hardware
Security Module, Functional Safety Hardware, and MJPEG encoder.

One peculiarity of this SoC is that the physical address of the DDDR
exceeds 32 bits. Given that the architecture is 64 bits, this is not
an issue, but it requires some changes in how the mips64 is currently
managed during boot.

In this seventh version, I removed the OLB related part as it is not
used yet. I have left it to Théo to handle in his series. Another
notable change is the Kconfig modification to remove the selection of
unused configurations.

To build and test the kernel, we need to run the following commands:

make eyeq5_defconfig
make vmlinuz.itb

Changelog:

 v6 -> v7

    - Added reviewed tags from Jiaxun Yang on patches 4 and 11.

    - Removed patch "dt-bindings: mfd: syscon: Document EyeQ5 OLB" as
      it is not used in this series.

    - Removed OLB node as it was not needed yet.

    - Fixed memory node and removed bootargs in dts on patch 11.

    - Modified the configuration selection as suggested by Jiaxun in
      patch 13.

 v5 -> v6:

    - From series v5, patches 1 ("MIPS: Export higher/highest
    relocation functions in uasm") and 3 ("MIPS: genex: Fix
    except_vec_vi for kernel in XKPHYS)" have been removed as "MIPS:
    Allow vectored interrupt handler to reside everywhere for 64bit"
    and "MIPS: Remove unused shadow GPR support from vector irq setup"
    address the same requirement.

    - From series v5, patches 8 to 12 have been removed as they are
    not mandatory to support EyeQ5 SoCs.

    - The 1st patch of series v6 ("MIPS: spaces: Define a couple of
    handy macros") has been modified to add the extra macros
    CKSEG[01]ADDR_OR_64BIT.

    - Patch 3 ("MIPS: Allows relocation exception vectors everywhere")
    is a merge of patches 6 ("MIPS: Refactor mips_cps_core_entry
    implementation) and 7 ("MIPS: Fix cache issue with
    mips_cps_core_entry") from series v5. It has been rewritten to
    reduce the diff stat; the 64-bit fixes have been moved to patch 5
    ("MIPS: cps-vec: Use macros for 64-bit access").

    - Patch 13 ("MIPS: Share generic kernel code with other
    architecture)" is a new one allowing separate platform support in
    the patch ("MIPS: Add support for Mobileye EyeQ5").

 v4 -> v5:

   - Improve commit messages for patch 3, 5, 12 and 13.

   - Fix style in patch 9

   - Really enable SPARSMEM and use correct address in
     board-eyeq5.config in patch 21

 v3 -> v4:

 - Fix build warning in "MIPS: Get rid of CONFIG_NO_EXCEPT_FILL":
   check that we are in 64bit mode before using KSEG0 that exist only
   in this mode.

 - Modify "MIPS: spaces: Define a couple of handy macros" to be
   buildable in 32bit mode.

 - Use correct format specifier to print address in "MIPS: traps: Give
   more explanations if ebase doesn't belong to KSEG0"

 - In "MIPS: generic: Add support for Mobileye EyeQ5",remove
   CONFIG_ZBOOT_LOAD_ADDRESS from board-eyeq5.config, (as well as
   CONFIG_USE_XKPHYS that does not exist anymore) and add
   CONFIG_SPARSEMEM_MANUAL to enable SPARSMEM.

v2 -> v3

 - Added more reviewed-by and acked-by tags

 - Fix sorting for cpus entries in

 - Fix indentation issue in Documentation/devicetree/bindings/mips/mobileye.yaml

 v1 -> v2

 - Added reviewed-by and acked-by tags

 - Fix typos reported

 - In patch 15 use 'img' vendor string instead of mti

 - In patch 16 modify licence

 - In patch 17 give more explanations about the block usage.

 - In patch 18, remove _ in node names, don't use anymore
   CONFIG_BUILTIN_DTB in Makefile, remove macro, modify licence.

 - In patch 19 remove most of the bootargs and only keeps earlycon. I
   also split the memory in 2 part in the device tree.

 - Integrate the series from Jiaxun Yang
   https://lore.kernel.org/linux-mips/20231027221106.405666-1-jiaxun.yang@flygoat.com/

  They are patches 2 to 6 and 8 to 12

  Then I added patch 7 to fix the cache issue visible on the Mobileye
  platform, I also add patch 13 to improve warning message when ebase
  doesn't belong to KSEG0

Regards,

Gregory

Gregory CLEMENT (12):
  MIPS: spaces: Define a couple of handy macros
  MIPS: traps: Give more explanations if ebase doesn't belong to KSEG0
  MIPS: cps-vec: Use macros for 64bits access
  dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd.
  dt-bindings: mips: cpus: Sort the entries
  dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
  dt-bindings: mips: Add bindings for Mobileye SoCs
  MIPS: mobileye: Add EyeQ5 dtsi
  MIPS: mobileye: Add EPM5 device tree
  MIPS: Share generic kernel code with other architecture
  MIPS: Add support for Mobileye EyeQ5
  MAINTAINERS: Add entry for Mobileye MIPS SoCs

Jiaxun Yang (2):
  MIPS: Fix set_uncached_handler for ebase in XKPHYS
  MIPS: Allows relocation exception vectors everywhere

 .../devicetree/bindings/mips/cpus.yaml        |  13 +-
 .../devicetree/bindings/mips/mobileye.yaml    |  32 ++
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS                                   |  12 +
 arch/mips/Kbuild                              |   1 +
 arch/mips/Kbuild.platforms                    |   1 +
 arch/mips/Kconfig                             |  57 ++++
 arch/mips/boot/dts/Makefile                   |   1 +
 arch/mips/boot/dts/mobileye/Makefile          |   4 +
 arch/mips/boot/dts/mobileye/eyeq5-epm5.dts    |  23 ++
 .../boot/dts/mobileye/eyeq5-fixed-clocks.dtsi | 292 ++++++++++++++++++
 arch/mips/boot/dts/mobileye/eyeq5.dtsi        | 124 ++++++++
 arch/mips/configs/eyeq5_defconfig             | 108 +++++++
 arch/mips/generic/Makefile                    |   6 +-
 arch/mips/include/asm/addrspace.h             |   5 +
 arch/mips/include/asm/mach-generic/spaces.h   |   4 +
 arch/mips/include/asm/mips-cm.h               |   1 +
 arch/mips/include/asm/smp-cps.h               |   4 +-
 arch/mips/kernel/cps-vec.S                    |  54 +---
 arch/mips/kernel/smp-cps.c                    | 171 ++++++++--
 arch/mips/kernel/traps.c                      |   7 +-
 arch/mips/mobileye/Makefile                   |   1 +
 arch/mips/mobileye/Platform                   |  16 +
 arch/mips/mobileye/board-epm5.its.S           |  24 ++
 arch/mips/mobileye/vmlinux.its.S              |  32 ++
 25 files changed, 914 insertions(+), 81 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mips/mobileye.yaml
 create mode 100644 arch/mips/boot/dts/mobileye/Makefile
 create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
 create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
 create mode 100644 arch/mips/boot/dts/mobileye/eyeq5.dtsi
 create mode 100644 arch/mips/configs/eyeq5_defconfig
 create mode 100644 arch/mips/mobileye/Makefile
 create mode 100644 arch/mips/mobileye/Platform
 create mode 100644 arch/mips/mobileye/board-epm5.its.S
 create mode 100644 arch/mips/mobileye/vmlinux.its.S

Comments

Jiaxun Yang Feb. 8, 2024, 9:38 a.m. UTC | #1 
在 2024/2/5 15:34, Gregory CLEMENT 写道:
> Some architectures might seek to utilize a significant portion of the
> generic kernel code while maintaining independence from the generic
> kernel due to specific peculiarities.
>
> This patch allows for the reuse of core code, preventing unnecessary
> duplication.
>
> Suggested-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Thanks!
- Jiaxun
> ---
>   arch/mips/Kbuild           | 1 +
>   arch/mips/Kconfig          | 3 +++
>   arch/mips/generic/Makefile | 6 +++---
>   3 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild
> index af2967bffb73d..d683993ed331c 100644
> --- a/arch/mips/Kbuild
> +++ b/arch/mips/Kbuild
> @@ -17,6 +17,7 @@ obj- := $(platform-y)
>   # mips object files
>   # The object files are linked as core-y files would be linked
>   
> +obj-y += generic/
>   obj-y += kernel/
>   obj-y += mm/
>   obj-y += net/
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 797ae590ebdba..5549d26448941 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -109,6 +109,9 @@ config MIPS_FIXUP_BIGPHYS_ADDR
>   config MIPS_GENERIC
>   	bool
>   
> +config MACH_GENERIC_CORE
> +	bool
> +
>   config MACH_INGENIC
>   	bool
>   	select SYS_SUPPORTS_32BIT_KERNEL
> diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile
> index e37a59bae0a62..56011d738441f 100644
> --- a/arch/mips/generic/Makefile
> +++ b/arch/mips/generic/Makefile
> @@ -4,9 +4,9 @@
>   # Author: Paul Burton <paul.burton@mips.com>
>   #
>   
> -obj-y += init.o
> -obj-y += irq.o
> -obj-y += proc.o
> +obj-$(CONFIG_MACH_GENERIC_CORE) += init.o
> +obj-$(CONFIG_MACH_GENERIC_CORE) += irq.o
> +obj-$(CONFIG_MACH_GENERIC_CORE) += proc.o
>   
>   obj-$(CONFIG_YAMON_DT_SHIM)		+= yamon-dt.o
>   obj-$(CONFIG_LEGACY_BOARD_SEAD3)	+= board-sead3.o
Jiaxun Yang Feb. 8, 2024, 9:38 a.m. UTC | #2 
在 2024/2/5 15:34, Gregory CLEMENT 写道:
> Introduce support for the MIPS based Mobileye EyeQ5 SoCs.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Thanks!
- Jiaxun
> ---
>   arch/mips/Kbuild.platforms          |   1 +
>   arch/mips/Kconfig                   |  54 ++++++++++++++
>   arch/mips/configs/eyeq5_defconfig   | 108 ++++++++++++++++++++++++++++
>   arch/mips/mobileye/Makefile         |   1 +
>   arch/mips/mobileye/Platform         |  16 +++++
>   arch/mips/mobileye/board-epm5.its.S |  24 +++++++
>   arch/mips/mobileye/vmlinux.its.S    |  32 +++++++++
>   7 files changed, 236 insertions(+)
>   create mode 100644 arch/mips/configs/eyeq5_defconfig
>   create mode 100644 arch/mips/mobileye/Makefile
>   create mode 100644 arch/mips/mobileye/Platform
>   create mode 100644 arch/mips/mobileye/board-epm5.its.S
>   create mode 100644 arch/mips/mobileye/vmlinux.its.S
>
> diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
> index a2311c4bce6a6..5c145b67d3bf4 100644
> --- a/arch/mips/Kbuild.platforms
> +++ b/arch/mips/Kbuild.platforms
> @@ -17,6 +17,7 @@ platform-$(CONFIG_MACH_LOONGSON2EF)	+= loongson2ef/
>   platform-$(CONFIG_MACH_LOONGSON32)	+= loongson32/
>   platform-$(CONFIG_MACH_LOONGSON64)	+= loongson64/
>   platform-$(CONFIG_MIPS_MALTA)		+= mti-malta/
> +platform-$(CONFIG_MACH_EYEQ5)		+= mobileye/
>   platform-$(CONFIG_MACH_NINTENDO64)	+= n64/
>   platform-$(CONFIG_PIC32MZDA)		+= pic32/
>   platform-$(CONFIG_RALINK)		+= ralink/
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 5549d26448941..a40eb9ecb50d5 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -569,6 +569,60 @@ config MACH_PIC32
>   	  Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>   	  microcontrollers.
>   
> +config MACH_EYEQ5
> +	bool "Mobileye EyeQ5 SoC"
> +	select MACH_GENERIC_CORE
> +	select ARM_AMBA
> +	select PHYSICAL_START_BOOL
> +	select ARCH_SPARSEMEM_DEFAULT if 64BIT
> +	select BOOT_RAW
> +	select BUILTIN_DTB
> +	select CEVT_R4K
> +	select CLKSRC_MIPS_GIC
> +	select COMMON_CLK
> +	select CPU_MIPSR2_IRQ_EI
> +	select CPU_MIPSR2_IRQ_VI
> +	select CSRC_R4K
> +	select DMA_NONCOHERENT
> +	select HAVE_PCI
> +	select IRQ_MIPS_CPU
> +	select MIPS_AUTO_PFN_OFFSET
> +	select MIPS_CPU_SCACHE
> +	select MIPS_GIC
> +	select MIPS_L1_CACHE_SHIFT_7
> +	select PCI_DRIVERS_GENERIC
> +	select SMP_UP if SMP
> +	select SWAP_IO_SPACE
> +	select SYS_HAS_CPU_MIPS64_R6
> +	select SYS_SUPPORTS_64BIT_KERNEL
> +	select SYS_SUPPORTS_HIGHMEM
> +	select SYS_SUPPORTS_LITTLE_ENDIAN
> +	select SYS_SUPPORTS_MIPS_CPS
> +	select SYS_SUPPORTS_RELOCATABLE
> +	select SYS_SUPPORTS_ZBOOT
> +	select UHI_BOOT
> +	select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
> +	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
> +	select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
> +	select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
> +	select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
> +	select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
> +	select USE_OF
> +	help
> +	  Select this to build a kernel supporting EyeQ5 SoC from Mobileye.
> +
> +	bool
> +
> +config FIT_IMAGE_FDT_EPM5
> +	bool "Include FDT for Mobileye EyeQ5 development platforms"
> +	depends on MACH_EYEQ5
> +	default n
> +	help
> +	  Enable this to include the FDT for the EyeQ5 development platforms
> +	  from Mobileye in the FIT kernel image.
> +	  This requires u-boot on the platform.
> +
> +
>   config MACH_NINTENDO64
>   	bool "Nintendo 64 console"
>   	select CEVT_R4K
> diff --git a/arch/mips/configs/eyeq5_defconfig b/arch/mips/configs/eyeq5_defconfig
> new file mode 100644
> index 0000000000000..c35c29a4d4795
> --- /dev/null
> +++ b/arch/mips/configs/eyeq5_defconfig
> @@ -0,0 +1,108 @@
> +CONFIG_SYSVIPC=y
> +CONFIG_NO_HZ_IDLE=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_BPF_SYSCALL=y
> +CONFIG_TASKSTATS=y
> +CONFIG_IKCONFIG=y
> +CONFIG_IKCONFIG_PROC=y
> +CONFIG_MEMCG=y
> +CONFIG_BLK_CGROUP=y
> +CONFIG_CFS_BANDWIDTH=y
> +CONFIG_RT_GROUP_SCHED=y
> +CONFIG_CGROUP_PIDS=y
> +CONFIG_CGROUP_FREEZER=y
> +CONFIG_CPUSETS=y
> +CONFIG_CGROUP_DEVICE=y
> +CONFIG_CGROUP_CPUACCT=y
> +CONFIG_NAMESPACES=y
> +CONFIG_USER_NS=y
> +CONFIG_SCHED_AUTOGROUP=y
> +CONFIG_BLK_DEV_INITRD=y
> +CONFIG_EXPERT=y
> +CONFIG_MACH_EYEQ5=y
> +CONFIG_FIT_IMAGE_FDT_EPM5=y
> +CONFIG_PAGE_SIZE_16KB=y
> +CONFIG_MIPS_CPS=y
> +CONFIG_CPU_HAS_MSA=y
> +CONFIG_NR_CPUS=16
> +CONFIG_MIPS_RAW_APPENDED_DTB=y
> +CONFIG_JUMP_LABEL=y
> +CONFIG_COMPAT_32BIT_TIME=y
> +CONFIG_MODULES=y
> +CONFIG_MODULE_UNLOAD=y
> +CONFIG_TRIM_UNUSED_KSYMS=y
> +# CONFIG_COMPAT_BRK is not set
> +CONFIG_SPARSEMEM_MANUAL=y
> +CONFIG_USERFAULTFD=y
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_NET_KEY=y
> +CONFIG_INET=y
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_NETFILTER=y
> +CONFIG_CAN=y
> +CONFIG_PCI=y
> +CONFIG_PCI_MSI=y
> +CONFIG_PCI_DEBUG=y
> +CONFIG_PCI_ENDPOINT=y
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
> +CONFIG_CONNECTOR=y
> +CONFIG_MTD=y
> +CONFIG_MTD_UBI=y
> +CONFIG_MTD_UBI_BLOCK=y
> +CONFIG_SCSI=y
> +CONFIG_NETDEVICES=y
> +CONFIG_MACVLAN=y
> +CONFIG_IPVLAN=y
> +CONFIG_MACB=y
> +CONFIG_MARVELL_PHY=y
> +CONFIG_MICREL_PHY=y
> +CONFIG_CAN_M_CAN=y
> +CONFIG_SERIAL_AMBA_PL011=y
> +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
> +CONFIG_HW_RANDOM=y
> +# CONFIG_PTP_1588_CLOCK is not set
> +CONFIG_PINCTRL=y
> +CONFIG_MFD_SYSCON=y
> +CONFIG_HID_A4TECH=y
> +CONFIG_HID_BELKIN=y
> +CONFIG_HID_CHERRY=y
> +CONFIG_HID_CYPRESS=y
> +CONFIG_HID_EZKEY=y
> +CONFIG_HID_ITE=y
> +CONFIG_HID_KENSINGTON=y
> +CONFIG_HID_REDRAGON=y
> +CONFIG_HID_MICROSOFT=y
> +CONFIG_HID_MONTEREY=y
> +CONFIG_MMC=y
> +CONFIG_MMC_SDHCI=y
> +# CONFIG_IOMMU_SUPPORT is not set
> +CONFIG_RESET_CONTROLLER=y
> +# CONFIG_NVMEM is not set
> +CONFIG_EXT4_FS=y
> +CONFIG_EXT4_FS_POSIX_ACL=y
> +CONFIG_EXT4_FS_SECURITY=y
> +CONFIG_FS_ENCRYPTION=y
> +CONFIG_FUSE_FS=y
> +CONFIG_CUSE=y
> +CONFIG_MSDOS_FS=y
> +CONFIG_VFAT_FS=y
> +CONFIG_TMPFS=y
> +CONFIG_TMPFS_POSIX_ACL=y
> +CONFIG_UBIFS_FS=y
> +CONFIG_NFS_FS=y
> +CONFIG_NFS_V3_ACL=y
> +CONFIG_NFS_V4=y
> +CONFIG_NFS_V4_1=y
> +CONFIG_NFS_V4_2=y
> +CONFIG_ROOT_NFS=y
> +CONFIG_CRYPTO_CRC32_MIPS=y
> +CONFIG_FRAME_WARN=1024
> +CONFIG_DEBUG_FS=y
> +# CONFIG_RCU_TRACE is not set
> +# CONFIG_FTRACE is not set
> +CONFIG_CMDLINE_BOOL=y
> +CONFIG_CMDLINE="earlycon"
> diff --git a/arch/mips/mobileye/Makefile b/arch/mips/mobileye/Makefile
> new file mode 100644
> index 0000000000000..315c06b689cfb
> --- /dev/null
> +++ b/arch/mips/mobileye/Makefile
> @@ -0,0 +1 @@
> +# SPDX-License-Identifier: GPL-2.0-or-later
> diff --git a/arch/mips/mobileye/Platform b/arch/mips/mobileye/Platform
> new file mode 100644
> index 0000000000000..43b6f4644592f
> --- /dev/null
> +++ b/arch/mips/mobileye/Platform
> @@ -0,0 +1,16 @@
> +#
> +# Copyright (C) 2016 Imagination Technologies
> +# Author: Paul Burton <paul.burton@mips.com>
> +#
> +# This program is free software; you can redistribute it and/or modify it
> +# under the terms of the GNU General Public License as published by the
> +# Free Software Foundation;  either version 2 of the  License, or (at your
> +# option) any later version.
> +#
> +
> +load-$(CONFIG_MACH_EYEQ5)	= 0xa800000808000000
> +all-$(CONFIG_MACH_EYEQ5)	+= vmlinux.gz.itb
> +
> +its-y					:= vmlinux.its.S
> +its-$(CONFIG_FIT_IMAGE_FDT_EPM5)	+= board-epm5.its.S
> +
> diff --git a/arch/mips/mobileye/board-epm5.its.S b/arch/mips/mobileye/board-epm5.its.S
> new file mode 100644
> index 0000000000000..08e8c4f183d63
> --- /dev/null
> +++ b/arch/mips/mobileye/board-epm5.its.S
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/ {
> +	images {
> +		fdt-mobileye-epm5 {
> +			description = "Mobileeye MP5 Device Tree";
> +			data = /incbin/("boot/dts/mobileye/eyeq5-epm5.dtb");
> +			type = "flat_dt";
> +			arch = "mips";
> +			compression = "none";
> +			hash {
> +				algo = "sha1";
> +			};
> +		};
> +	};
> +
> +    configurations {
> +		default = "conf-1";
> +		conf-1 {
> +			description = "Mobileye EPM5 Linux kernel";
> +			kernel = "kernel";
> +			fdt = "fdt-mobileye-epm5";
> +		};
> +	};
> +};
> diff --git a/arch/mips/mobileye/vmlinux.its.S b/arch/mips/mobileye/vmlinux.its.S
> new file mode 100644
> index 0000000000000..3e254676540f4
> --- /dev/null
> +++ b/arch/mips/mobileye/vmlinux.its.S
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/dts-v1/;
> +
> +/ {
> +	description = KERNEL_NAME;
> +	#address-cells = <ADDR_CELLS>;
> +
> +	images {
> +		kernel {
> +			description = KERNEL_NAME;
> +			data = /incbin/(VMLINUX_BINARY);
> +			type = "kernel";
> +			arch = "mips";
> +			os = "linux";
> +			compression = VMLINUX_COMPRESSION;
> +			load = /bits/ ADDR_BITS <VMLINUX_LOAD_ADDRESS>;
> +			entry = /bits/ ADDR_BITS <VMLINUX_ENTRY_ADDRESS>;
> +			hash {
> +				algo = "sha1";
> +			};
> +		};
> +	};
> +
> +	configurations {
> +		default = "conf-default";
> +
> +		conf-default {
> +			description = "Generic Linux kernel";
> +			kernel = "kernel";
> +		};
> +	};
> +};
Thomas Bogendoerfer Feb. 8, 2024, 12:11 p.m. UTC | #3 
On Mon, Feb 05, 2024 at 04:34:49PM +0100, Gregory CLEMENT wrote:
> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
> 
> Now the exception vector for CPS systems are allocated on-fly
> with memblock as well.
> 
> It will try to allocate from KSEG1 first, and then try to allocate
> in low 4G if possible.
> 
> The main reset vector is now generated by uasm, to avoid tons
> of patches to the code. Other vectors are copied to the location
> later.
> 
> gc: use the new macro CKSEG[0A1]DDR_OR_64BIT()
>     move 64bits fix in an other patch
>     fix cache issue with mips_cps_core_entry
>     rewrite the patch to reduce the diff stat
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
>  arch/mips/include/asm/mips-cm.h |   1 +
>  arch/mips/include/asm/smp-cps.h |   4 +-
>  arch/mips/kernel/cps-vec.S      |  48 ++-------
>  arch/mips/kernel/smp-cps.c      | 171 +++++++++++++++++++++++++++-----
>  4 files changed, 157 insertions(+), 67 deletions(-)
> [..]
> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
> index dd55d59b88db3..f4cdd50177e0b 100644
> --- a/arch/mips/kernel/smp-cps.c
> +++ b/arch/mips/kernel/smp-cps.c
> @@ -7,6 +7,7 @@
>  #include <linux/cpu.h>
>  #include <linux/delay.h>
>  #include <linux/io.h>
> +#include <linux/memblock.h>
>  #include <linux/sched/task_stack.h>
>  #include <linux/sched/hotplug.h>
>  #include <linux/slab.h>
> @@ -25,7 +26,34 @@
>  #include <asm/time.h>
>  #include <asm/uasm.h>
>  
> +#define BEV_VEC_SIZE	0x500
> +#define BEV_VEC_ALIGN	0x1000
> +
> +#define A0		4
> +#define A1		5
> +#define T9		25
> +#define K0		26
> +#define K1		27
> +
> +#define C0_STATUS	12, 0
> +#define C0_CAUSE	13, 0
> +
> +#define ST0_NMI_BIT	19
> +#ifdef CONFIG_64BIT
> +#define ST0_KX_IF_64	ST0_KX
> +#else
> +#define ST0_KX_IF_64	0
> +#endif

please move this together with the other defines in arch/mips/kvm/entry.c
to a header file (arch/mips/include/asm/uasm.h sounds like a good fit).

> +static void __init setup_cps_vecs(void)
> +{
> +	extern void excep_tlbfill(void);
> +	extern void excep_xtlbfill(void);
> +	extern void excep_cache(void);
> +	extern void excep_genex(void);
> +	extern void excep_intex(void);
> +	extern void excep_ejtag(void);

I know this used a lot in arch/mips, but don't add another one and
put this to a header file. IMHO checkpatch should have warned you about
that.

> +	/* We want to ensure cache is clean before writing uncached mem */
> +	blast_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE);
> +	bc_wback_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE);
> +	__sync();

how about doint the generation with cached memory and flush caches
after that ?

Thomas.
Thomas Bogendoerfer Feb. 8, 2024, 12:14 p.m. UTC | #4 
On Mon, Feb 05, 2024 at 04:34:47PM +0100, Gregory CLEMENT wrote:
> Define KSEGX_SIZE to represent the size of each KSEG segment.
> 
> Introduce CKSEG0ADDR_OR_64BIT and CKSEG1ADDR_OR_64BIT to get an XPHYS
> address in 64bits and CKSEG[01]ADDR() in 32 bits mode.
> 
> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
>  arch/mips/include/asm/addrspace.h           | 5 +++++
>  arch/mips/include/asm/mach-generic/spaces.h | 4 ++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
> index 59a48c60a065c..03a5e2c8b5dc9 100644
> --- a/arch/mips/include/asm/addrspace.h
> +++ b/arch/mips/include/asm/addrspace.h
> @@ -47,6 +47,11 @@
>   */
>  #define KSEGX(a)		((_ACAST32_(a)) & _ACAST32_(0xe0000000))
>  
> +/*
> + * Gives the size of each kernel segment
> + */
> +#define KSEGX_SIZE		0x20000000

well this is the KSEG size for 32bit and defined in a common section,
so better use CSEGX_SIZE

Thomas.
Thomas Bogendoerfer Feb. 8, 2024, 12:18 p.m. UTC | #5 
On Mon, Feb 05, 2024 at 04:34:46PM +0100, Gregory CLEMENT wrote:
> Hello,
> 
> The EyeQ5 SoC from Mobileye is based on the MIPS I6500 architecture
> and features multiple controllers such as the classic UART, I2C, SPI,
> as well as CAN-FD, PCIe, Octal/Quad SPI Flash interface, Gigabit
> Ethernet, MIPI CSI-2, and eMMC 5.1. It also includes a Hardware
> Security Module, Functional Safety Hardware, and MJPEG encoder.
> 
> One peculiarity of this SoC is that the physical address of the DDDR
> exceeds 32 bits. Given that the architecture is 64 bits, this is not
> an issue, but it requires some changes in how the mips64 is currently
> managed during boot.
> 
> In this seventh version, I removed the OLB related part as it is not
> used yet. I have left it to Théo to handle in his series. Another
> notable change is the Kconfig modification to remove the selection of
> unused configurations.
> [..]

thank you for your work on this patch set. I've commented on the
two patches, where is see need for changes. Other than that it's
looking good.

Thomas.
Gregory CLEMENT Feb. 14, 2024, 4:44 p.m. UTC | #6 
Thomas Bogendoerfer <tsbogend@alpha.franken.de> writes:

> On Mon, Feb 05, 2024 at 04:34:47PM +0100, Gregory CLEMENT wrote:
>> Define KSEGX_SIZE to represent the size of each KSEG segment.
>> 
>> Introduce CKSEG0ADDR_OR_64BIT and CKSEG1ADDR_OR_64BIT to get an XPHYS
>> address in 64bits and CKSEG[01]ADDR() in 32 bits mode.
>> 
>> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>>  arch/mips/include/asm/addrspace.h           | 5 +++++
>>  arch/mips/include/asm/mach-generic/spaces.h | 4 ++++
>>  2 files changed, 9 insertions(+)
>> 
>> diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
>> index 59a48c60a065c..03a5e2c8b5dc9 100644
>> --- a/arch/mips/include/asm/addrspace.h
>> +++ b/arch/mips/include/asm/addrspace.h
>> @@ -47,6 +47,11 @@
>>   */
>>  #define KSEGX(a)		((_ACAST32_(a)) & _ACAST32_(0xe0000000))
>>  
>> +/*
>> + * Gives the size of each kernel segment
>> + */
>> +#define KSEGX_SIZE		0x20000000
>
> well this is the KSEG size for 32bit and defined in a common section,
> so better use CSEGX_SIZE

Done in the next series.

Thanks,

Gregory


>
> Thomas.
>
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]
Gregory CLEMENT Feb. 14, 2024, 4:48 p.m. UTC | #7 
Thomas Bogendoerfer <tsbogend@alpha.franken.de> writes:

> On Mon, Feb 05, 2024 at 04:34:49PM +0100, Gregory CLEMENT wrote:
>> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> 
>> Now the exception vector for CPS systems are allocated on-fly
>> with memblock as well.
>> 
>> It will try to allocate from KSEG1 first, and then try to allocate
>> in low 4G if possible.
>> 
>> The main reset vector is now generated by uasm, to avoid tons
>> of patches to the code. Other vectors are copied to the location
>> later.
>> 
>> gc: use the new macro CKSEG[0A1]DDR_OR_64BIT()
>>     move 64bits fix in an other patch
>>     fix cache issue with mips_cps_core_entry
>>     rewrite the patch to reduce the diff stat
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>>  arch/mips/include/asm/mips-cm.h |   1 +
>>  arch/mips/include/asm/smp-cps.h |   4 +-
>>  arch/mips/kernel/cps-vec.S      |  48 ++-------
>>  arch/mips/kernel/smp-cps.c      | 171 +++++++++++++++++++++++++++-----
>>  4 files changed, 157 insertions(+), 67 deletions(-)
>> [..]
>> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
>> index dd55d59b88db3..f4cdd50177e0b 100644
>> --- a/arch/mips/kernel/smp-cps.c
>> +++ b/arch/mips/kernel/smp-cps.c
>> @@ -7,6 +7,7 @@
>>  #include <linux/cpu.h>
>>  #include <linux/delay.h>
>>  #include <linux/io.h>
>> +#include <linux/memblock.h>
>>  #include <linux/sched/task_stack.h>
>>  #include <linux/sched/hotplug.h>
>>  #include <linux/slab.h>
>> @@ -25,7 +26,34 @@
>>  #include <asm/time.h>
>>  #include <asm/uasm.h>
>>  
>> +#define BEV_VEC_SIZE	0x500
>> +#define BEV_VEC_ALIGN	0x1000
>> +
>> +#define A0		4
>> +#define A1		5
>> +#define T9		25
>> +#define K0		26
>> +#define K1		27
>> +
>> +#define C0_STATUS	12, 0
>> +#define C0_CAUSE	13, 0
>> +
>> +#define ST0_NMI_BIT	19
>> +#ifdef CONFIG_64BIT
>> +#define ST0_KX_IF_64	ST0_KX
>> +#else
>> +#define ST0_KX_IF_64	0
>> +#endif
>
> please move this together with the other defines in arch/mips/kvm/entry.c
> to a header file (arch/mips/include/asm/uasm.h sounds like a good fit).


Jiaxun Yang sent a series to address it [1]. I managed to rebase my
series on top of this one.

Do you agree with these 8 patches?

Can I send my next series with the assumption that it will be merged?

Gregory

1: https://lore.kernel.org/linux-mips/20240209-regname-v1-0-2125efa016ef@flygoat.com/
Thomas Bogendoerfer Feb. 14, 2024, 7:14 p.m. UTC | #8 
On Wed, Feb 14, 2024 at 05:48:51PM +0100, Gregory CLEMENT wrote:
> Jiaxun Yang sent a series to address it [1]. I managed to rebase my
> series on top of this one.
> 
> Do you agree with these 8 patches?

first glance looked good ;-)

> Can I send my next series with the assumption that it will be merged?

yes, I'll start applying next week.

Thomas.